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Paper Abstract and Keywords
Presentation 2012-11-28 10:30
A Hardware Algorithm Using Dynamically Partially Reconfigurable FPGAs for Solving the Maximum Clique Problem of Large Graphs
Chikako Miura, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) RECONF2012-53
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a hardware algorithm to solve the maximum clique problem of large graphs, and show its implementation results using a dynamically partially reconfigurable FPGA.
Although existing hardware algorithms cannot solve the problem for graphs with many nodes due to the resource limitation on an FPGA, the proposed algorithm can solve the problem for such large graphs using only one FPGA by generating subgraphs from a given graph, and implementing them using dynamically partial reconfiguration of an FPGA.
Since the proposed hardware algorithm is based on a branch-and-bound method, it can explore solution space efficiently, and reduce the number of partial reconfigurations of FPGA.
Our experimental results using a dynamically partially reconfigurable FPGA show that the proposed algorithm can efficiently solve the problem that an existing algorithm cannot solve.
Keyword (in Japanese) (See Japanese page) 
(in English) maximum clique problem / branch-and-bound method / FPGA / partial reconfiguration / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 325, RECONF2012-53, pp. 33-38, Nov. 2012.
Paper # RECONF2012-53 
Date of Issue 2012-11-20 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2012-11-26 - 2012-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Centennial Hall Kyushu University School of Medicine 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2012 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Hardware Algorithm Using Dynamically Partially Reconfigurable FPGAs for Solving the Maximum Clique Problem of Large Graphs 
Sub Title (in English)  
Keyword(1) maximum clique problem  
Keyword(2) branch-and-bound method  
Keyword(3) FPGA  
Keyword(4) partial reconfiguration  
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1st Author's Name Chikako Miura  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Shinobu Nagayama  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Shin'ichi Wakabayashi  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Masato Inagi  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker
Date Time 2012-11-28 10:30:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2012-53 
Volume (vol) IEICE-112 
Number (no) no.325 
Page pp.33-38 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2012-11-20 


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