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Paper Abstract and Keywords
Presentation 2012-11-28 13:25
A 3D FPGA-Array HPC System "Vocalise" and its Performance Evaluation
Yusuke Atsumari, Jiang Li, Hiromasa Kubo, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2012-94 DC2012-60
Abstract (in Japanese) (See Japanese page) 
(in English) We have developed a 10cm square card with a three-dimensional I/O that installed a 4 million system gate scale FPGA and have already confirmed its basic operation. We are building a High Performance Computing (HPC) system constituted by connecting the card in the shape of a three-dimensional array. We called that HPC system as a Virtual Object by Configurable Array of Little Scalable Engine (Vocalise). In this report, the communication circuit of this HPC system is described. In addition, we implement a Poisson's equation arithmetic circuit on the system, and report its operation performance and power consumption.
Keyword (in Japanese) (See Japanese page) 
(in English) Vocalise / FPGA-Array / Reconfigurable HPC / Poisson's equation / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 320, VLD2012-94, pp. 201-206, Nov. 2012.
Paper # VLD2012-94 
Date of Issue 2012-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2012-94 DC2012-60

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2012-11-26 - 2012-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Centennial Hall Kyushu University School of Medicine 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2012 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 3D FPGA-Array HPC System "Vocalise" and its Performance Evaluation 
Sub Title (in English)  
Keyword(1) Vocalise  
Keyword(2) FPGA-Array  
Keyword(3) Reconfigurable HPC  
Keyword(4) Poisson's equation  
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1st Author's Name Yusuke Atsumari  
1st Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
2nd Author's Name Jiang Li  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
3rd Author's Name Hiromasa Kubo  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
4th Author's Name Hakaru Tamukoh  
4th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
5th Author's Name Masatoshi Sekine  
5th Author's Affiliation Tokyo University of Agriculture and Technology (TUAT)
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Speaker Author-1 
Date Time 2012-11-28 13:25:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2012-94, DC2012-60 
Volume (vol) vol.112 
Number (no) no.320(VLD), no.321(DC) 
Page pp.201-206 
#Pages
Date of Issue 2012-11-19 (VLD, DC) 


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