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Paper Abstract and Keywords
Presentation 2012-11-28 14:30
Energy Measurement and Analysis of ProcessingElement for Ultra Low Voltage
Sachio Anzai, Masaru Kudo, Yuya Ota, Kazuki Ota, Kimiyoshi Usami (Sibaura Inst. Tech.) VLD2012-99 DC2012-65
Abstract (in Japanese) (See Japanese page) 
(in English) The ALU of the ProcessingElement at 65nm process was operated by the ultra-low voltage, and delay time and survey of power consumption were performed. The minimum operating voltage of each arithmetic circuit was 0.18V when chip temperature was 25 ℃ and 45 ℃, 0.19V at 65 ℃, and in the adder and the logic operation circuit,0.19V, and 0.20V in the multiplication circuit and the shift arithmetic circuit at 85 ℃. Moreover, the voltage from which the consumption energy in 25 ℃ serves as the minimum was 0.32V in the summing circuit and the logic operation circuit, was 0.34V in the multiplication circuit, and was 0.30V in the shift arithmetic circuit. As for each computing unit, the voltage from which energy serves as the minimum in connection with temperature rising also became high.
Keyword (in Japanese) (See Japanese page) 
(in English) ProcessingElement / Ultra Low Voltage / Low Power Technique / / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 320, VLD2012-99, pp. 231-236, Nov. 2012.
Paper # VLD2012-99 
Date of Issue 2012-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2012-99 DC2012-65

Conference Information
Conference Date 2012-11-26 - 2012-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Centennial Hall Kyushu University School of Medicine 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2012 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Energy Measurement and Analysis of ProcessingElement for Ultra Low Voltage 
Sub Title (in English)  
Keyword(1) ProcessingElement  
Keyword(2) Ultra Low Voltage  
Keyword(3) Low Power Technique  
1st Author's Name Sachio Anzai  
1st Author's Affiliation Shibaura Institute of Technology (Sibaura Inst. Tech.)
2nd Author's Name Masaru Kudo  
2nd Author's Affiliation Shibaura Institute of Technology (Sibaura Inst. Tech.)
3rd Author's Name Yuya Ota  
3rd Author's Affiliation Shibaura Institute of Technology (Sibaura Inst. Tech.)
4th Author's Name Kazuki Ota  
4th Author's Affiliation Shibaura Institute of Technology (Sibaura Inst. Tech.)
5th Author's Name Kimiyoshi Usami  
5th Author's Affiliation Shibaura Institute of Technology (Sibaura Inst. Tech.)
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Date Time 2012-11-28 14:30:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2012-99,IEICE-DC2012-65 
Volume (vol) IEICE-112 
Number (no) no.320(VLD), no.321(DC) 
Page pp.231-236 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2012-11-19,IEICE-DC-2012-11-19 

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