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| Presentation | 2012-11-28 09:50 Performance evaluation of Via Programmable Logic VPEX using P&R tool Taku Otani, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ), Masaya Yoshikawa (Meijo Univ), Takeshi Fujino (Ritsumeikan Univ)  VLD2012-90 DC2012-56 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We have been studying via programmable structured ASIC architecture “VPEX” which can realize arbitrary logic by customizing via layer. We have made performance evaluations of area and delay using logic synthesis tool. In this paper, we have established a layout design flow using IC Compiler in order to evaluate these performances and power performance more accurately. There are two design flows; one is a “standard ASIC flow” in which normal standard cell is used, and another is “pseudo-VPEX flow” in which logic element of VPEX is used as a placement cell. The area, delay and power performance of VPEX are evaluated by PrimeTime, and compared with ASIC and structured ASIC architecture VCLB (Via-Configurable Logic Block) which was proposed in Yuan-Ze University. As a result, the area of VPEX is estimated as 2.5 times that of ASIC and as half of VCLB which is 5 times that of ASIC. The power consumption of VPEX is 1.3-4.5 times as large as that of ASIC, and as same as that of VCLB. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Via Programmable / structured ASIC / Exclusive-OR / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 320, VLD2012-90, pp. 177-182, Nov. 2012. | |
| Paper # | VLD2012-90 | |
| Date of Issue | 2012-11-19 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2012-90 DC2012-56 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2012-11-26 - 2012-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Centennial Hall Kyushu University School of Medicine |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2012 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance evaluation of Via Programmable Logic VPEX using P&R tool |
| Sub Title (in English) | |
| Keyword(1) | Via Programmable |
| Keyword(2) | structured ASIC |
| Keyword(3) | Exclusive-OR |
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| 1st Author's Name | Taku Otani |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ) |
| 2nd Author's Name | Ryohei Hori |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ) |
| 3rd Author's Name | Taisuke Ueoka |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ) |
| 4th Author's Name | Masaya Yoshikawa |
| 4th Author's Affiliation | Meijo University (Meijo Univ) |
| 5th Author's Name | Takeshi Fujino |
| 5th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ) |
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| Speaker | Author-1 |
| Date Time | 2012-11-28 09:50:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2012-90, DC2012-56 |
| Volume (vol) | vol.112 |
| Number (no) | no.320(VLD), no.321(DC) |
| Page | pp.177-182 |
| #Pages | 6 |
| Date of Issue | 2012-11-19 (VLD, DC) |
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