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| Presentation | 2012-11-27 17:00 [Keynote Address] Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics)  VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 Link to ES Tech. Rep. Archives: CPM2012-117 ICD2012-81 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | DRP features two dimensional array of tiny processors and memories, onto which applications are compiled and mapped as a hardware structure that reflects original nature of data and control flow of the application. We have ceaselessly conducted its R&D and business development from late 1990, resulted in wide product deployment especially in image processing equipments recently. On the way, we needed number of breakthroughs and dense R&D efforts not only in architecture and circuit design for achieving orders of magnitude better performance/power over conventional CPU, but also product-quality IP core technologies (testing, cost-reduction, etc.), integrated design tool (compiler) which features high-level synthesis tool as its core technology, middleware like drivers/API, product-level application development, and proving all of them. This talk will trace historical developments of such R&D efforts, analyze what have been most crucial on its way, and will also reveal its current standpoint. In view of the severe troubles that today’s VLSI’s face, namely 1) engineering issues due to continuously increasing power dissipation, e.g., power wall and utilization wall, 2) economical issues where low-volume chips cannot amortize ever rising chip cost anymore, it will also be argued that reconfigurable architectures like our DRP is going to have more and more practical importance. Finally, remaining issues to be solved for truly wider acceptance of the type of technology will be discussed. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Reconfigurable / Programmable / Dynamic Reconfiguration / High-Level Synthesis / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 320, VLD2012-87, pp. 163-163, Nov. 2012. | |
| Paper # | VLD2012-87 | |
| Date of Issue | 2012-11-19 (VLD, CPSY, DC), 2012-11-20 (CPM, ICD, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 Link to ES Tech. Rep. Archives: CPM2012-117 ICD2012-81 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2012-11-26 - 2012-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Centennial Hall Kyushu University School of Medicine |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2012 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable |
| Keyword(2) | Programmable |
| Keyword(3) | Dynamic Reconfiguration |
| Keyword(4) | High-Level Synthesis |
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| 1st Author's Name | Masato Motomura |
| 1st Author's Affiliation | Hokkaido University (Hokkaido Univ.) |
| 2nd Author's Name | Koichiro Furuta |
| 2nd Author's Affiliation | Renesas Electronics Corporation (Renesas Electronics) |
| 3rd Author's Name | Toru Awashima |
| 3rd Author's Affiliation | Renesas Electronics Corporation (Renesas Electronics) |
| 4th Author's Name | Yasunari Shida |
| 4th Author's Affiliation | Renesas Electronics Corporation (Renesas Electronics) |
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| Speaker | Author-1 |
| Date Time | 2012-11-27 17:00:00 |
| Presentation Time | 60 minutes |
| Registration for | VLD |
| Paper # | VLD2012-87, CPM2012-117, ICD2012-81, CPSY2012-55, DC2012-53, RECONF2012-49 |
| Volume (vol) | vol.112 |
| Number (no) | no.320(VLD), no.323(CPM), no.324(ICD), no.322(CPSY), no.321(DC), no.325(RECONF) |
| Page | p.163(VLD), p.29(CPM), p.29(ICD), p.45(CPSY), p.163(DC), p.15(RECONF) |
| #Pages | 1 |
| Date of Issue | 2012-11-19 (VLD, CPSY, DC), 2012-11-20 (CPM, ICD, RECONF) |
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