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| Presentation | 2012-11-27 10:55 A Behavioral Synthesis Method for Asynchronous Pipelined Circuits with Bundled-data Implementation Naohiro Hamada, Hiroshi Saito (The Univ. of Aizu)  VLD2012-77 DC2012-43 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we propose behavioral synthesis methods for asynchronous pipelined circuits with bundled-data implementation. Proposed methods synthesize asynchronous pipelined circuits with two different schemes. One is a behavioral synthesis method which considers characteristics of asynchronous pipelined circuits. Another is a combination of a data-path synthesis for synchronous pipelined circuits and a control synthesis for asynchronous pipelined circuits. Through the synthesis of several benchmarks, we evaluate the effectiveness of two proposed methods. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Asynchronous pipelined circuits / Behavioral synthesis / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 320, VLD2012-77, pp. 105-110, Nov. 2012. | |
| Paper # | VLD2012-77 | |
| Date of Issue | 2012-11-19 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2012-77 DC2012-43 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2012-11-26 - 2012-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Centennial Hall Kyushu University School of Medicine |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2012 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Behavioral Synthesis Method for Asynchronous Pipelined Circuits with Bundled-data Implementation |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous pipelined circuits |
| Keyword(2) | Behavioral synthesis |
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| 1st Author's Name | Naohiro Hamada |
| 1st Author's Affiliation | The University of Aizu (The Univ. of Aizu) |
| 2nd Author's Name | Hiroshi Saito |
| 2nd Author's Affiliation | The University of Aizu (The Univ. of Aizu) |
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| Speaker | Author-1 |
| Date Time | 2012-11-27 10:55:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2012-77, DC2012-43 |
| Volume (vol) | vol.112 |
| Number (no) | no.320(VLD), no.321(DC) |
| Page | pp.105-110 |
| #Pages | 6 |
| Date of Issue | 2012-11-19 (VLD, DC) |
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