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| Presentation | 2012-11-27 09:50 An ILP Formulation of Placement and Routing for PLDs Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ)  VLD2012-75 DC2012-41 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we formulate the simultaneous technology mapping, placement and routing problem for programmable gate arrays (PLDs) as an integer liner programming (ILP) problem, and obtain the exact optimal solutions using an ILP solver. Each of technology mapping, placement and routing for PLDs (e.g., FPGA) usually employs a heuristic method to obtain a good solution within a practical time, and a lot of heuristic methods have been being studied. However, there is no guarantee that they find a good solution. Furthermore, division of circuit design process affects the quality of the final solution. Thus, it is expected that exact optimal solutions of circuit design help the development of a heuristic method. Experimental results showed that exact optimal solutions can be obtained for small circuits. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | PLD / FPGA / technology mapping / placement and routing / exact optimal solution / ILP / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 320, VLD2012-75, pp. 93-98, Nov. 2012. | |
| Paper # | VLD2012-75 | |
| Date of Issue | 2012-11-19 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2012-75 DC2012-41 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2012-11-26 - 2012-11-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Centennial Hall Kyushu University School of Medicine |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2012 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2012-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An ILP Formulation of Placement and Routing for PLDs |
| Sub Title (in English) | |
| Keyword(1) | PLD |
| Keyword(2) | FPGA |
| Keyword(3) | technology mapping |
| Keyword(4) | placement and routing |
| Keyword(5) | exact optimal solution |
| Keyword(6) | ILP |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hiroki Nishiyama |
| 1st Author's Affiliation | Hiroshima City University (Hiroshima City Univ) |
| 2nd Author's Name | Masato Inagi |
| 2nd Author's Affiliation | Hiroshima City University (Hiroshima City Univ) |
| 3rd Author's Name | Shin'ichi Wakabayashi |
| 3rd Author's Affiliation | Hiroshima City University (Hiroshima City Univ) |
| 4th Author's Name | Shinobu Nagayama |
| 4th Author's Affiliation | Hiroshima City University (Hiroshima City Univ) |
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| Speaker | Author-1 |
| Date Time | 2012-11-27 09:50:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2012-75, DC2012-41 |
| Volume (vol) | vol.112 |
| Number (no) | no.320(VLD), no.321(DC) |
| Page | pp.93-98 |
| #Pages | 6 |
| Date of Issue | 2012-11-19 (VLD, DC) |
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