| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2012-10-19 09:25 Design of a Packet-Transfer-Based Dynamic Reconfigurable VLSI Processor for Reduction of a Configuration Memory Size Yoshichika Fujioka (Hachinohe Inst. of Tech.), Michitaka Kameyama (Tohoku Univ.)  VLD2012-47 SIP2012-69 ICD2012-64 IE2012-71 Link to ES Tech. Rep. Archives: ICD2012-64 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration memory for dynamically reconfigurable VLSI processors greatly reduced. Configuration memory reduction in the conventional dynamically reconfigurable parallel VLSI processor can be achieved based on semi-autonomous packet routing, where both autonomous packet data transfer and offline scheduling/allocation are effectively utilized. It is demonstrated that we can make the control storage size much smaller than the conventional dynamically reconfigurable VLSI, even in the case where the CDFG contains many conditional branches. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | coarse-grain reconfigurable VLSI processor / semi-autonomous packet routing / configuration memory / conditional branches / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 247, ICD2012-64, pp. 39-44, Oct. 2012. | |
| Paper # | ICD2012-64 | |
| Date of Issue | 2012-10-11 (VLD, SIP, ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2012-47 SIP2012-69 ICD2012-64 IE2012-71 Link to ES Tech. Rep. Archives: ICD2012-64 |
|
| Conference Information | |
| Committee | IE SIP ICD VLD IPSJ-SLDM |
| Conference Date | 2012-10-18 - 2012-10-19 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hotel Ruiz |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2012-10-IE-SIP-ICD-VLD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of a Packet-Transfer-Based Dynamic Reconfigurable VLSI Processor for Reduction of a Configuration Memory Size |
| Sub Title (in English) | |
| Keyword(1) | coarse-grain reconfigurable VLSI processor |
| Keyword(2) | semi-autonomous packet routing |
| Keyword(3) | configuration memory |
| Keyword(4) | conditional branches |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yoshichika Fujioka |
| 1st Author's Affiliation | Hachinohe Institute of Technology (Hachinohe Inst. of Tech.) |
| 2nd Author's Name | Michitaka Kameyama |
| 2nd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 3rd Author's Name | |
| 3rd Author's Affiliation | () |
| 4th Author's Name | |
| 4th Author's Affiliation | () |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| 7th Author's Name | |
| 7th Author's Affiliation | () |
| 8th Author's Name | |
| 8th Author's Affiliation | () |
| 9th Author's Name | |
| 9th Author's Affiliation | () |
| 10th Author's Name | |
| 10th Author's Affiliation | () |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2012-10-19 09:25:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | VLD2012-47, SIP2012-69, ICD2012-64, IE2012-71 |
| Volume (vol) | vol.112 |
| Number (no) | no.245(VLD), no.246(SIP), no.247(ICD), no.248(IE) |
| Page | pp.39-44 |
| #Pages | 6 |
| Date of Issue | 2012-10-11 (VLD, SIP, ICD, IE) |
[Return to Top Page]