Paper Abstract and Keywords |
Presentation |
2012-10-19 13:50
A Low Power CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling (DVFS) and Adaptively Assigned Breaking-off Condition (A2BC) Motion Estimation Algorithm Tadayoshi Enomoto, Nobuaki Kobayashi (Chuo Univ) VLD2012-53 SIP2012-75 ICD2012-70 IE2012-77 Link to ES Tech. Rep. Archives: ICD2012-70 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) technique to greatly reduce the power dissipation. To make full use of the advantages of DVFS technique, a fast ME algorithm was also developed. It can adaptively predict the optimum supply voltage and the optimum clock frequency before ME process starts for each macro-block for encoding. Power dissipation of the 90-nm CMOS DVFS controlled ME processor, which contained an absolute difference accumulator as well as a small on-chip DC/DC level converter, a minimum value detector and DVFS controller, was reduced to 73.6µW, which was only 1.02% that of a conventional ME processor. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
motion estimation processor / power dissipation / H.264/AVC / DVFS / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 248, IE2012-77, pp. 71-76, Oct. 2012. |
Paper # |
IE2012-77 |
Date of Issue |
2012-10-11 (VLD, SIP, ICD, IE) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2012-53 SIP2012-75 ICD2012-70 IE2012-77 Link to ES Tech. Rep. Archives: ICD2012-70 |
Conference Information |
Committee |
IE SIP ICD VLD IPSJ-SLDM |
Conference Date |
2012-10-18 - 2012-10-19 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hotel Ruiz |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
IE |
Conference Code |
2012-10-IE-SIP-ICD-VLD-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Low Power CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling (DVFS) and Adaptively Assigned Breaking-off Condition (A2BC) Motion Estimation Algorithm |
Sub Title (in English) |
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Keyword(1) |
motion estimation processor |
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power dissipation |
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H.264/AVC |
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DVFS |
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1st Author's Name |
Tadayoshi Enomoto |
1st Author's Affiliation |
Chuo University (Chuo Univ) |
2nd Author's Name |
Nobuaki Kobayashi |
2nd Author's Affiliation |
Chuo University (Chuo Univ) |
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Speaker |
Author-1 |
Date Time |
2012-10-19 13:50:00 |
Presentation Time |
25 minutes |
Registration for |
IE |
Paper # |
VLD2012-53, SIP2012-75, ICD2012-70, IE2012-77 |
Volume (vol) |
vol.112 |
Number (no) |
no.245(VLD), no.246(SIP), no.247(ICD), no.248(IE) |
Page |
pp.71-76 |
#Pages |
6 |
Date of Issue |
2012-10-11 (VLD, SIP, ICD, IE) |
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