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| Presentation | 2012-10-19 13:00 Accelerator Architecture for Multi Scale Filter Operation Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)  VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 Link to ES Tech. Rep. Archives: ICD2012-68 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Image recognition processing includes a number of filter operations which dominate the total execution time. Exploiting ALU array to accelerate the filter operations is one of the most promising approaches to achieve such energy-efficient executions. However, it is difficult for conventional ALU array accelerator to achieve high-performance and low-energy for multi-scale filter operations. To tackle this issule this paper proposes DSP (Data Stream Processing) tile accelerator for multi scale filter operations. Tile accelerator has many DSP tiles which can execute a small size of filter efficiently. Each DSP tile is connected with three-dimensionally implemented scratch-pad memories via TSVs. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Accelerator / Reconfigurable-Processor / Image Recognition / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 247, ICD2012-68, pp. 59-64, Oct. 2012. | |
| Paper # | ICD2012-68 | |
| Date of Issue | 2012-10-11 (VLD, SIP, ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 Link to ES Tech. Rep. Archives: ICD2012-68 |
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| Conference Information | |
| Committee | IE SIP ICD VLD IPSJ-SLDM |
| Conference Date | 2012-10-18 - 2012-10-19 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hotel Ruiz |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2012-10-IE-SIP-ICD-VLD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Accelerator Architecture for Multi Scale Filter Operation |
| Sub Title (in English) | |
| Keyword(1) | Accelerator |
| Keyword(2) | Reconfigurable-Processor |
| Keyword(3) | Image Recognition |
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| 1st Author's Name | Shinya Ueno |
| 1st Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 2nd Author's Name | Gauthier Lovic Eric |
| 2nd Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 3rd Author's Name | Koji Inoue |
| 3rd Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 4th Author's Name | Kazuaki Murakami |
| 4th Author's Affiliation | Kyushu University (Kyushu Univ.) |
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| Speaker | Author-1 |
| Date Time | 2012-10-19 13:00:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | VLD2012-51, SIP2012-73, ICD2012-68, IE2012-75 |
| Volume (vol) | vol.112 |
| Number (no) | no.245(VLD), no.246(SIP), no.247(ICD), no.248(IE) |
| Page | pp.59-64 |
| #Pages | 6 |
| Date of Issue | 2012-10-11 (VLD, SIP, ICD, IE) |
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