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Paper Abstract and Keywords
Presentation 2012-09-19 13:15
A Design Framework for Reconfigurable IPs with VLSI CADs
Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-41
Abstract (in Japanese) (See Japanese page) 
(in English) The conventional FPGA design CAD flows evaluate FPGA architecture by implementing benchmarks through the following steps: synthesis, technology mapping, clustering and placement and routing (P&R). The area and timing performance reports are derived from the P&R tool. The accuracy of the result is low but proved to be enough to evaluate architectures fairly. However, for complete FPGA IP design, the architecture should be evaluated with standard cell by full back-end design flow. We proposed a new FPGA routing tool, namely EasyRouter. By using simple HDL templates, the Easy Router can automatically generate entire device's verilogs and bitstream according to architecture definition and routing result. With these files, the FPGA IP can be evaluated with commercial VLSD CADs in high accuracy and reliability.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / CAD / Routing / / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 203, RECONF2012-41, pp. 101-106, Sept. 2012.
Paper # RECONF2012-41 
Date of Issue 2012-09-11 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee RECONF  
Conference Date 2012-09-18 - 2012-09-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Epock Ritsumei 21, Ritsumeikan Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2012-09-RECONF 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Design Framework for Reconfigurable IPs with VLSI CADs 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) CAD  
Keyword(3) Routing  
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1st Author's Name Qian Zhao  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Kazuki Inoue  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Motoki Amagasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Toshinori Sueyoshi  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker
Date Time 2012-09-19 13:15:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2012-41 
Volume (vol) IEICE-112 
Number (no) no.203 
Page pp.101-106 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2012-09-11 


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