講演抄録/キーワード |
講演名 |
2012-09-19 13:15
A Design Framework for Reconfigurable IPs with VLSI CADs ○Qian Zhao・Kazuki Inoue・Motoki Amagasaki・Masahiro Iida・Toshinori Sueyoshi(Kumamoto Univ.) RECONF2012-41 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
The conventional FPGA design CAD flows evaluate FPGA architecture by implementing benchmarks through the following steps: synthesis, technology mapping, clustering and placement and routing (P&R). The area and timing performance reports are derived from the P&R tool. The accuracy of the result is low but proved to be enough to evaluate architectures fairly. However, for complete FPGA IP design, the architecture should be evaluated with standard cell by full back-end design flow. We proposed a new FPGA routing tool, namely EasyRouter. By using simple HDL templates, the Easy Router can automatically generate entire device's verilogs and bitstream according to architecture definition and routing result. With these files, the FPGA IP can be evaluated with commercial VLSD CADs in high accuracy and reliability. |
キーワード |
(和) |
/ / / / / / / |
(英) |
FPGA / CAD / Routing / / / / / |
文献情報 |
信学技報, vol. 112, no. 203, RECONF2012-41, pp. 101-106, 2012年9月. |
資料番号 |
RECONF2012-41 |
発行日 |
2012-09-11 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
RECONF2012-41 |
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