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Paper Abstract and Keywords
Presentation 2012-09-18 15:15
An Area Minimized Logic Cluster using COGRE Logic Cell
Toshiya Takahashi, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-32
Abstract (in Japanese) (See Japanese page) 
(in English) These days, FPGAs (Field Programmable Gate Arrays) is required to increase in size and performance
in order to deal with complicated systems.
To increase in size and performance of FPGAs,
we proposed two ideas in previous work.
The first is a small-memory logic cell; COGRE (Compactly Organized Generic Reconfigurable Element) ,
the second is the method of input-sharing between BLEs (Basic Logic Elements ) .
In this paper, we propose a new approach to combine these two ideas.
The experimental results show that the product of area and delay of our proposed logic block is 42% smaller than that of the traditional one.
Further, we find out that our proposed logic block is quite high performance as compared with the COGRE based logic block.
Keyword (in Japanese) (See Japanese page) 
(in English) logic block / COGRE / local interconnect / / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 203, RECONF2012-32, pp. 49-54, Sept. 2012.
Paper # RECONF2012-32 
Date of Issue 2012-09-11 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2012-32

Conference Information
Committee RECONF  
Conference Date 2012-09-18 - 2012-09-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Epock Ritsumei 21, Ritsumeikan Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2012-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Area Minimized Logic Cluster using COGRE Logic Cell 
Sub Title (in English)  
Keyword(1) logic block  
Keyword(2) COGRE  
Keyword(3) local interconnect  
1st Author's Name Toshiya Takahashi  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Kazuki Inoue  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Motoki Amagasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Morihiro Kuga  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
6th Author's Name Toshinori Sueyoshi  
6th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Date Time 2012-09-18 15:15:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2012-32 
Volume (vol) IEICE-112 
Number (no) no.203 
Page pp.49-54 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2012-09-11 

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