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| Presentation | 2012-09-18 13:20 [Invited Talk] The LSI Design Methodology of Tamper Resistant Cryptographic Circuit Takeshi Fujino, Mitsuru Shiozaki, Takaya Kubota (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Uiv.)  RECONF2012-29 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Tamper LSI Design Methodology have to be applied in order to implement secure cryptographic circuit which is resistant to side-channel attack such as DPA (Differential Power Analysis). The principle of DPA, some typical countermeasures against DPA, and the problem on the LSI implementation are introduced in this paper. The “dual-rail RSL memory” which consumes constant power irrespective of input/output value, is developed. The cryptographic design methodology, in which the “dual-rail RSL memory” is used on a non-linear circuit, and the additive masked logic using XOR gate is used on a linear circuit, is easy to be implemented on SoC, because these methods are easy to be implemented in the conventional LSI design flow. The AES cryptographic circuit, which is the most popular cryptographic algolithm, was designed in 0.18 um CMOS technology. The test chip demonstrates the high tamper resistance against power analysis. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Tamper Resistant LSI / Side-Channel Attack / AES / DPA / CPA / WDDL / RSL / Dual-rail RSL Memory | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 203, RECONF2012-29, pp. 31-36, Sept. 2012. | |
| Paper # | RECONF2012-29 | |
| Date of Issue | 2012-09-11 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2012-29 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2012-09-18 - 2012-09-19 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Epock Ritsumei 21, Ritsumeikan Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2012-09-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The LSI Design Methodology of Tamper Resistant Cryptographic Circuit |
| Sub Title (in English) | |
| Keyword(1) | Tamper Resistant LSI |
| Keyword(2) | Side-Channel Attack |
| Keyword(3) | AES |
| Keyword(4) | DPA |
| Keyword(5) | CPA |
| Keyword(6) | WDDL |
| Keyword(7) | RSL |
| Keyword(8) | Dual-rail RSL Memory |
| 1st Author's Name | Takeshi Fujino |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name | Mitsuru Shiozaki |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 3rd Author's Name | Takaya Kubota |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 4th Author's Name | Masaya Yoshikawa |
| 4th Author's Affiliation | Meijyo University (Meijyo Uiv.) |
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| Speaker | Author-1 |
| Date Time | 2012-09-18 13:20:00 |
| Presentation Time | 50 minutes |
| Registration for | RECONF |
| Paper # | RECONF2012-29 |
| Volume (vol) | vol.112 |
| Number (no) | no.203 |
| Page | pp.31-36 |
| #Pages | 6 |
| Date of Issue | 2012-09-11 (RECONF) |
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