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Paper Abstract and Keywords
Presentation 2012-09-18 16:30
Study of "fine-grain dynamic partial reconfiguration mechanism" on FPGA
Kunihiro Ueda, Naoki Kawamoto, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2012-34
Abstract (in Japanese) (See Japanese page) 
(in English) Dynamic and partial reconfiguration (DRP) on SRAM-based FPGAs has received increasing attention, since Xilinx Inc. started official support for design with DRP in 2010. However, in this design flow, every FPGA bit stream used for DRP must be generated in advance using an EDA tool. In this paper, aiming at enabling a more flexible DRP framework, we investigate a DRP reconfiguration in which the FPGA itself generates bit streams for reconfiguration on the fly, mainly targeting on LUT-based fine-grained reconfiguration. The proposed method is evaluated from the viewpoints of power consumption and configuration time.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / dynamic partial reconfiguration / power consumption / / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 203, RECONF2012-34, pp. 61-66, Sept. 2012.
Paper # RECONF2012-34 
Date of Issue 2012-09-11 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee RECONF  
Conference Date 2012-09-18 - 2012-09-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Epock Ritsumei 21, Ritsumeikan Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2012-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Study of "fine-grain dynamic partial reconfiguration mechanism" on FPGA 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) dynamic partial reconfiguration  
Keyword(3) power consumption  
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1st Author's Name Kunihiro Ueda  
1st Author's Affiliation Nagasaki University (Nagasaki Univ.)
2nd Author's Name Naoki Kawamoto  
2nd Author's Affiliation Nagasaki University (Nagasaki Univ.)
3rd Author's Name Keisuke Dohi  
3rd Author's Affiliation Nagasaki University (Nagasaki Univ.)
4th Author's Name Yuichiro Shibata  
4th Author's Affiliation Nagasaki University (Nagasaki Univ.)
5th Author's Name Kiyoshi Oguri  
5th Author's Affiliation Nagasaki University (Nagasaki Univ.)
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Speaker
Date Time 2012-09-18 16:30:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2012-34 
Volume (vol) IEICE-112 
Number (no) no.203 
Page pp.61-66 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2012-09-11 


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