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| Presentation | 2012-08-02 17:30 Proposal of performance model for block ciphers using GPGPU Naoki Nishikawa, Keisuke Iwai, Takakazu Kurokawa (NDA)  CPSY2012-16 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we present a prototype of performance model of block ciphers using GPGPU whose encryption latency is readily predictable before the implementation. Essential point of the performance model is that block cipher algorithms optimized in software are comprised of only three components (table access, extended key access, and logical operations). Herein, to test the prototype briefly on CUDA GPUs, we assumed that the latency of the logical operations is hidden under that of the memory accesses if adequate number of threads are running. Applying the model on two generations (Fermi and GT200) of six CUDA GPUs, the error values of AES and Camellia between the estimated and measured latencies were 10.5 % and 17.5 % at the maximum, respectively. The reason for the difference of the error is because the number of logical operations in Camellia is third times that in AES; and then the logical operation latency was not completely hidden under the memory accesses | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | GPGPU / CUDA / Block Cipher / Performance Model / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 173, CPSY2012-16, pp. 43-48, Aug. 2012. | |
| Paper # | CPSY2012-16 | |
| Date of Issue | 2012-07-26 (CPSY) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2012-16 |
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| Conference Information | |
| Committee | DC CPSY |
| Conference Date | 2012-08-02 - 2012-08-03 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Torigin Bunka Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Summer United Workshops on Parallel, Distributed and Cooperative Processing "Tottori" (SWoPP 2012) |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2012-08-DC-CPSY |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Proposal of performance model for block ciphers using GPGPU |
| Sub Title (in English) | |
| Keyword(1) | GPGPU |
| Keyword(2) | CUDA |
| Keyword(3) | Block Cipher |
| Keyword(4) | Performance Model |
| Keyword(5) | |
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| 1st Author's Name | Naoki Nishikawa |
| 1st Author's Affiliation | National Defense Academy of Japan (NDA) |
| 2nd Author's Name | Keisuke Iwai |
| 2nd Author's Affiliation | National Defense Academy of Japan (NDA) |
| 3rd Author's Name | Takakazu Kurokawa |
| 3rd Author's Affiliation | National Defense Academy of Japan (NDA) |
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| Speaker | Author-1 |
| Date Time | 2012-08-02 17:30:00 |
| Presentation Time | 30 minutes |
| Registration for | CPSY |
| Paper # | CPSY2012-16 |
| Volume (vol) | vol.112 |
| Number (no) | no.173 |
| Page | pp.43-48 |
| #Pages | 6 |
| Date of Issue | 2012-07-26 (CPSY) |
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