| 講演抄録／キーワード |
| 講演名 |
2012-06-28 10:40
［ポスター講演］Rigorous Design for Gate-Dielectric and n-Pocket Region of Tunneling Field-Effect Transistors and Its High Performances.
○Jae Hwa Seo・Jae Sung Lee・Yun Soo Park・Jung-Hee Lee・In Man Kang（Kyunpook Nat'l Univ.） エレソ技報アーカイブはこちら |
| 抄録 |
（和） |
A gate-all-around tunneling field-effect transistor (GAA TFET) with high-k gate-dielectric and n-pocket layer is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-pocket layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, on-current can be increased compared with conventional TFET. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) and n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off- current (Ion, Ioff), subthreshold swing (SS), and RF performances. |
| （英） |
A gate-all-around tunneling field-effect transistor (GAA TFET) with high-k gate-dielectric and n-pocket layer is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-pocket layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) and n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off- current (Ion and Ioff), subthreshold swing (SS), and RF performances. |
| キーワード |
（和） |
gate-all-around (GAA) / tunneling field-effect transistor (TFET) / n-pocket layer / / / / / |
| （英） |
gate-all-around (GAA) / tunneling field-effect transistor (TFET) / n-pocket layer / / / / / |
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信学技報 |
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