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| Presentation | 2012-05-29 16:00 An Efficient Fault Detection and Avoidance Technique for FPGA Interconnects Yuuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)  RECONF2012-13 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | FPGA's fault detection needs a great deal of test time as compared with ASIC because FPGAs have complex structures and programmability. Moreover, the operation of both re-placement and re-routing must be performed to avoid fault points. These operations cause the increase of recovery time and degrades performance. In this paper, we propose a fault detection method and develop placement and routing tools to avoid fault resources in tile and multiplexer level avoidance, respectively. The evaluation of the detection method diagnosed a faulty multiplexer by six test con gurations. We found out that the performance of faulty FPGA can curb the decline up to 2% as compared with the normal FPGA in multiplexer level avoidance. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Fault detection / Fault avoidance / Fault tolerant technique / FPGA / Reconfigurable system / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 70, RECONF2012-13, pp. 71-76, May 2012. | |
| Paper # | RECONF2012-13 | |
| Date of Issue | 2012-05-22 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Notes on Review | This article is a technical report without peer review, and its polished version will be published elsewhere. | |
| Download PDF | RECONF2012-13 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2012-05-29 - 2012-05-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tiruru (Naha Okinawa, Japan) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2012-05-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Efficient Fault Detection and Avoidance Technique for FPGA Interconnects |
| Sub Title (in English) | |
| Keyword(1) | Fault detection |
| Keyword(2) | Fault avoidance |
| Keyword(3) | Fault tolerant technique |
| Keyword(4) | FPGA |
| Keyword(5) | Reconfigurable system |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yuuki Nishitani |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 2nd Author's Name | Kazuki Inoue |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 4th Author's Name | Morihiro Kuga |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 5th Author's Name | Masahiro Iida |
| 5th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 6th Author's Name | Toshinori Sueyoshi |
| 6th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2012-05-29 16:00:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2012-13 |
| Volume (vol) | vol.112 |
| Number (no) | no.70 |
| Page | pp.71-76 |
| #Pages | 6 |
| Date of Issue | 2012-05-22 (RECONF) |
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