Paper Abstract and Keywords |
Presentation |
2012-04-24 11:15
[Invited Talk]
Write-/Read- Disturb Issues and Circuit Solutions Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki (Renesas Electronics) ICD2012-11 Link to ES Tech. Rep. Archives: ICD2012-11 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper describes some circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage against write-/read-disturb issues and a new test screening circuit with synchronous clock to detect the worst Vmin in asynchronous clock operation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
dual-port / Embedded SRAM / 8T / 28nm / write disturb / read disturb / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 15, ICD2012-11, pp. 55-60, April 2012. |
Paper # |
ICD2012-11 |
Date of Issue |
2012-04-16 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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Download PDF |
ICD2012-11 Link to ES Tech. Rep. Archives: ICD2012-11 |