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Paper Abstract and Keywords
Presentation 2012-04-24 14:15
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura (Kobe Univ.), Toshikazu Suzuki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) Link to ES Tech. Rep. Archives: ICD2012-14
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-micron SRAM macro. The classic write-back scheme overcame a half-select problem and improved a yield; however, the conventional scheme consumed more power due to charging and discharging all write bitlines (WBLs) in a sub block. Our proposed scheme consists of a floating bitline technique and a low-swing bitline driver (LSBD). This scheme decreases active leakage and active power by 33% and 37% at the FF corner, respectively. In other process corners, more active power reduction can be expected. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The proposed scheme achieves 1.52-W/MHz active energy in a write cycle and 72.8-W leakage power, which are 59.4% and 26.0% better than the conventional write-back scheme. The total energy is 12.9 W/MHz at 0.5 V in a 50%-read / 50%-write operation.
Keyword (in Japanese) (See Japanese page) 
(in English) SRAM / 8T / disturb / half-select / write back / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 15, ICD2012-14, pp. 73-78, April 2012.
Paper # ICD2012-14 
Date of Issue 2012-04-16 (ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Conference Information
Committee ICD  
Conference Date 2012-04-23 - 2012-04-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Seion-so, Tsunagi Hot Spring (Iwate) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Memory Device Technologies 
Paper Information
Registration To ICD 
Conference Code 2012-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme 
Sub Title (in English)  
Keyword(1) SRAM  
Keyword(2) 8T  
Keyword(3) disturb  
Keyword(4) half-select  
Keyword(5) write back  
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1st Author's Name Shusuke Yoshimoto  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Masaharu Terada  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Shunsuke Okumura  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Toshikazu Suzuki  
4th Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
5th Author's Name Shinji Miyano  
5th Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
6th Author's Name Hiroshi Kawaguchi  
6th Author's Affiliation Kobe University (Kobe Univ.)
7th Author's Name Masahiko Yoshimoto  
7th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker
Date Time 2012-04-24 14:15:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-ICD2012-14 
Volume (vol) IEICE-112 
Number (no) no.15 
Page pp.73-78 
#Pages IEICE-6 
Date of Issue IEICE-ICD-2012-04-16 


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