Paper Abstract and Keywords |
Presentation |
2012-04-23 12:30
[Invited Talk]
A 19nm 112.8mm2 64Gb Multi-level(2bit/cell) Flash Memory with 400Mb/s/pin 1.8V Toggle Mode Interface Noboru Shibata, Kazushige Kanda, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yuui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, Kazuko Inuzuka, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, Jiyun Nakai (Toshiba), Teruhiko Kamei (SanDisk) ICD2012-1 Link to ES Tech. Rep. Archives: ICD2012-1 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A 64Gb MLC NAND flash memory on 19nm CMOS technology has been developed. By adopting One-Sided All-Bit-Line architecture and Single-Array configuration, 112.8mm2 die size is realized. 15MB/s program throughput with high reliability 2bits/cell is achieved using Bit-Line Bias Acceleration (BLBA) and “BC”-States-First program algorithm. Program-Suspend and Erase-Suspend functions are introduced to reduce read latency. This device also supports 400MT/s 1.8V high speed Toggle Mode interface. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
NAND flash memory / 19nm CMOS technology / MLC(2bit/cell) / Toggle Mode / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 112, no. 15, ICD2012-1, pp. 1-5, April 2012. |
Paper # |
ICD2012-1 |
Date of Issue |
2012-04-16 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2012-1 Link to ES Tech. Rep. Archives: ICD2012-1 |
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