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Paper Abstract and Keywords
Presentation 2012-04-10 13:25
Method for routing in a mixed topology of 3-D NoC
Daisuke Sasaki, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII/Souken Univ./JST), Hideharu Amano (Keio Univ.) CPSY2012-2 DC2012-2
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we evaluate a deadlock-free routing strategy in 3-D
NoCs that consist of chips with heterogeneous NoCs and those with
homogeneous NoCs.
To guarantee deadlock-freedom in the 3-D NoC, the routing strategy
uses dimension-order routing for chips with mesh- or torus-based NoCs
while Up*/Down* routing for chips with heterogeneous NoCs.
Evaluation results show that the proposed routing strategy improves
the network throughput by 10% compared to Up*/Down* routing.
Keyword (in Japanese) (See Japanese page) 
(in English) 3-D Netowork-on-Chip(NoC) / routing algorithm / mixed topology network / / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 2, CPSY2012-2, pp. 7-12, April 2012.
Paper # CPSY2012-2 
Date of Issue 2012-04-03 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2012-2 DC2012-2

Conference Information
Committee CPSY DC  
Conference Date 2012-04-10 - 2012-04-10 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CPSY 
Conference Code 2012-04-CPSY-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Method for routing in a mixed topology of 3-D NoC 
Sub Title (in English)  
Keyword(1) 3-D Netowork-on-Chip(NoC)  
Keyword(2) routing algorithm  
Keyword(3) mixed topology network  
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1st Author's Name Daisuke Sasaki  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Hiroki Matsutani  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Michihiro Koibuchi  
3rd Author's Affiliation National Institute of Informatics/The Graduate University for Advanced Studies/JST (NII/Souken Univ./JST)
4th Author's Name Hideharu Amano  
4th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2012-04-10 13:25:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2012-2, DC2012-2 
Volume (vol) vol.112 
Number (no) no.2(CPSY), no.3(DC) 
Page pp.7-12 
#Pages
Date of Issue 2012-04-03 (CPSY, DC) 


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