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| Presentation | 2012-04-10 13:00 A Processor to Tolerate Periodical Transient Faults under Highly Electromagnetic Environment by Using Built in Self Test Masahiko Negishi, Aromhack Saysanasongkham, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.)  CPSY2012-1 DC2012-1 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper releases a report of the application for the fault tolerant sequential circuit technique against the periodical transient faults under highly electromagnetic environment which we have proposed in the previous paper. As an example for utility-scale of sequential circuits, the result obtained by applying the proposed technique to simple processor is shown. By means of logic simulation, we confirm that an 8-bits processor originally designed with functional BIST can avoid the periodical multiple transient faults. We further show that the sequential circuit about the size of processors can be applied the fault tolerant technique at low overhead from the viewpoint of the circuit space. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | transient fault tolerant circuit / on-line functional BIST / electromagnetic radiation / DC-AC inverter / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 112, no. 2, CPSY2012-1, pp. 1-6, April 2012. | |
| Paper # | CPSY2012-1 | |
| Date of Issue | 2012-04-03 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2012-1 DC2012-1 |
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| Conference Information | |
| Committee | CPSY DC |
| Conference Date | 2012-04-10 - 2012-04-10 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2012-04-CPSY-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Processor to Tolerate Periodical Transient Faults under Highly Electromagnetic Environment by Using Built in Self Test |
| Sub Title (in English) | |
| Keyword(1) | transient fault tolerant circuit |
| Keyword(2) | on-line functional BIST |
| Keyword(3) | electromagnetic radiation |
| Keyword(4) | DC-AC inverter |
| Keyword(5) | |
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| Keyword(8) | |
| 1st Author's Name | Masahiko Negishi |
| 1st Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
| 2nd Author's Name | Aromhack Saysanasongkham |
| 2nd Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
| 3rd Author's Name | Masayuki Arai |
| 3rd Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
| 4th Author's Name | Satoshi Fukumoto |
| 4th Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2012-04-10 13:00:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | CPSY2012-1, DC2012-1 |
| Volume (vol) | vol.112 |
| Number (no) | no.2(CPSY), no.3(DC) |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2012-04-03 (CPSY, DC) |
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