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| Presentation | 2012-03-09 14:10 A Memory Controller with Guaranteed-Bandwidth Solution Hisashi Iwamoto, Yasuto Kuroda, Yuji Yano (Renesas), Koji Yamamoto (RDC), Shingo Ata (Osaka City Univ.), kazunari Inoue (Nara National College of Tec./Osaka Univ.)  NS2011-258 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Network traffic keeps increasing like as the demand of video streaming. Routers and switches in wire-line networks require guaranteed line rate as high as 20Gbp/s as well as advanced quality of service (QoS). This paper proposes an intelligent memory management unit (MMU), wherever 16k multi queues are integrated. The performance examined by the system board is zero-packet loss under the seamless traffic with 60-1.5kByte packet-length.(deterministic manner) The intelligent MMU involves head buffer architecture, which is suitable to support a large numbers of FIFO queues. The experimental board based on this architecture is embedded into a Router system to evaluate the performance. Using 16k queues at 20Gbps, zero-packet loss is examined with 64-Byte to 1,500-Byte packet-length. Keyword IP Router, Packet Buffer, Memory-Controller, Guaranteed-bandwidth. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | IP Router / Packet Buffer / Memory-Controller / Guaranteed-bandwidth / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 468, NS2011-258, pp. 445-450, March 2012. | |
| Paper # | NS2011-258 | |
| Date of Issue | 2012-03-01 (NS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | NS2011-258 |
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| Conference Information | |
| Committee | NS IN |
| Conference Date | 2012-03-08 - 2012-03-09 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Miyazaki Seagia |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | General |
| Paper Information | |
| Registration To | NS |
| Conference Code | 2012-03-NS-IN |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Memory Controller with Guaranteed-Bandwidth Solution |
| Sub Title (in English) | |
| Keyword(1) | IP Router |
| Keyword(2) | Packet Buffer |
| Keyword(3) | Memory-Controller |
| Keyword(4) | Guaranteed-bandwidth |
| Keyword(5) | |
| Keyword(6) | |
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| Keyword(8) | |
| 1st Author's Name | Hisashi Iwamoto |
| 1st Author's Affiliation | Renesas Electronics (Renesas) |
| 2nd Author's Name | Yasuto Kuroda |
| 2nd Author's Affiliation | Renesas Electronics (Renesas) |
| 3rd Author's Name | Yuji Yano |
| 3rd Author's Affiliation | Renesas Electronics (Renesas) |
| 4th Author's Name | Koji Yamamoto |
| 4th Author's Affiliation | Renesas Design (RDC) |
| 5th Author's Name | Shingo Ata |
| 5th Author's Affiliation | Osaka City University (Osaka City Univ.) |
| 6th Author's Name | kazunari Inoue |
| 6th Author's Affiliation | Nara national Collegeof Technology/Osaka University (Nara National College of Tec./Osaka Univ.) |
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| Speaker | Author-2 |
| Date Time | 2012-03-09 14:10:00 |
| Presentation Time | 20 minutes |
| Registration for | NS |
| Paper # | NS2011-258 |
| Volume (vol) | vol.111 |
| Number (no) | no.468 |
| Page | pp.445-450 |
| #Pages | 6 |
| Date of Issue | 2012-03-01 (NS) |
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