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Paper Abstract and Keywords
Presentation 2012-03-08 14:10
A Low-Jitter 1.5-GHz and Large-EMI reduction 10-dBm Spread-Spectrum Clock Generator for Serial-ATA
Takashi Kawamoto (Hitachi), Masato Suzuki (Renesas) CAS2011-129 SIP2011-149 CS2011-121
Abstract (in Japanese) (See Japanese page) 
(in English) A low-jitter and large-EMI-reduction spread spectrum clock generator (SSCG) for Serial-ATA (SATA) was developed. A low-jitter voltage-controlled oscillator (VCO) with a high-frequency limiter was developed to prevent the SSCG from malfunctioning. This VCO achieved far less jitter than that of a conventional VCO. An auto-calibration technique suitable for this VCO was developed to prevent the SSCG from degrading performance because of process variations. A SATA-PHY using a technique for calibrating the SSCG was developed to use an inexpensive but large frequency-variation reference oscillator. This technique was used to calibrate the SSCG output-signal frequency. This is achieved by shifting an SSCG divide ratio by utilizing the difference between an SSCG output signal frequency and a received signal frequency. These techniques were fabricated in 0.13- and 0.15-um CMOS processes. The proposed SSCG achieved a 10.0-dB reduction in EMI. The variation in the rms jitter at 1.5 GHz with spread-spectrum clocking was reduced from 2.1-7.8 ps to 1.9-3.3 ps by the proposed autocalibration technique. The proposed SATA PHY achieved less than 400-ppm production-frequency tolerance of reference clocks.
Keyword (in Japanese) (See Japanese page) 
(in English) SSCG / CDR / PLL / Serial-ATA / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 465, CAS2011-129, pp. 125-130, March 2012.
Paper # CAS2011-129 
Date of Issue 2012-03-01 (CAS, SIP, CS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Download PDF CAS2011-129 SIP2011-149 CS2011-121

Conference Information
Committee CAS CS SIP  
Conference Date 2012-03-08 - 2012-03-09 
Place (in Japanese) (See Japanese page) 
Place (in English) The University of Niigata 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Network Processor, Signal Processing for communication, and Wireless LAN/PAN, etc. 
Paper Information
Registration To CAS 
Conference Code 2012-03-CAS-CS-SIP 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Low-Jitter 1.5-GHz and Large-EMI reduction 10-dBm Spread-Spectrum Clock Generator for Serial-ATA 
Sub Title (in English)  
Keyword(1) SSCG  
Keyword(2) CDR  
Keyword(3) PLL  
Keyword(4) Serial-ATA  
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1st Author's Name Takashi Kawamoto  
1st Author's Affiliation Hitachi (Hitachi)
2nd Author's Name Masato Suzuki  
2nd Author's Affiliation Reness Electronics (Renesas)
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Speaker Author-1 
Date Time 2012-03-08 14:10:00 
Presentation Time 25 minutes 
Registration for CAS 
Paper # CAS2011-129, SIP2011-149, CS2011-121 
Volume (vol) vol.111 
Number (no) no.465(CAS), no.466(SIP), no.467(CS) 
Page pp.125-130 
#Pages
Date of Issue 2012-03-01 (CAS, SIP, CS) 


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