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Paper Abstract and Keywords
Presentation 2012-03-08 13:45
A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique
Masanori Furuta, Taichi Ogawa, Tetsuro Itakura (Toshiba)
Abstract (in Japanese) (See Japanese page) 
(in English) An eight-channel time-interleaved ADC with individual reference voltage buffers is presented. Each channel consists of buffer amplifier and two successive approximation ADC (SAR ADC) in a pipeline configuration. The proposed architecture shares an amplifier between the voltage buffer and the residue amplifier. The amplifier sharing technique achieves better isolation between the individual channels while minimizing the additional circuit. Over one bit redundancy is implemented to compensate the process variation of the MOM capacitance.
Fabricated in 65nm CMOS with an active area of 0.36mm^2, the prototype chip achieves a peak SNDR of 32.3dB(single-channel) at 60MS/s and 26dB(time-interleave) at 480MS/s sampling rate and has a power consumption of 6mW.
Keyword (in Japanese) (See Japanese page) 
(in English) Time-interleaved / SAR / ADC / low-power / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 465, CAS2011-128, pp. 121-124, March 2012.
Paper # CAS2011-128 
Date of Issue 2012-03-01 (CAS, SIP, CS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee CAS CS SIP  
Conference Date 2012-03-08 - 2012-03-09 
Place (in Japanese) (See Japanese page) 
Place (in English) The University of Niigata 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Network Processor, Signal Processing for communication, and Wireless LAN/PAN, etc. 
Paper Information
Registration To CAS 
Conference Code 2012-03-CAS-CS-SIP 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique 
Sub Title (in English)  
Keyword(1) Time-interleaved  
Keyword(2) SAR  
Keyword(3) ADC  
Keyword(4) low-power  
1st Author's Name Masanori Furuta  
1st Author's Affiliation Toshiba Corporation (Toshiba)
2nd Author's Name Taichi Ogawa  
2nd Author's Affiliation Toshiba Corporation (Toshiba)
3rd Author's Name Tetsuro Itakura  
3rd Author's Affiliation Toshiba Corporation (Toshiba)
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Date Time 2012-03-08 13:45:00 
Presentation Time 25 
Registration for CAS 
Paper # IEICE-CAS2011-128,IEICE-SIP2011-148,IEICE-CS2011-120 
Volume (vol) IEICE-111 
Number (no) no.465(CAS), no.466(SIP), no.467(CS) 
Page pp.121-124 
#Pages IEICE-4 
Date of Issue IEICE-CAS-2012-03-01,IEICE-SIP-2012-03-01,IEICE-CS-2012-03-01 

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