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Paper Abstract and Keywords
Presentation 2012-03-07 13:20
Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor
Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.)
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes a DVFS technique to reduce energy dissipation of Dynamically Reconfigurable Processors(DRP). DRP’s behaviors are categorized into Contexts Writing mode and Executing mode, and the operation is decided by contexts. In this study, we designed memory circuits in which contexts are written, and applied this technique to a part of operation circuit and memory circuit in this processor. Then we propose a method that controls V_DD and frequency to this processor which has a system which is necessary in order to apply this technique. As a result, it has been shown that it can decrease the number of V_DD switching, and it can reduce approximately 49% at the maximum in Contexts Writing mode and approximately 46% at the maximum in Executing mode energy dissipation when benchmark application of three types is used.
Keyword (in Japanese) (See Japanese page) 
(in English) Dynamically Reconfigurable Processor / Low Power Technique / DVFS / SRAM / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 450, VLD2011-138, pp. 109-114, March 2012.
Paper # VLD2011-138 
Date of Issue 2012-02-28 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee VLD  
Conference Date 2012-03-06 - 2012-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) B-con Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Methodologies for System-on-a-chip 
Paper Information
Registration To VLD 
Conference Code 2012-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor 
Sub Title (in English)  
Keyword(1) Dynamically Reconfigurable Processor  
Keyword(2) Low Power Technique  
Keyword(3) DVFS  
Keyword(4) SRAM  
1st Author's Name Yuki Hayakawa  
1st Author's Affiliation Shibaura Institute of Technology (Shibaura Institute of Tech.)
2nd Author's Name Kimiyoshi Usami  
2nd Author's Affiliation Shibaura Institute of Technology (Shibaura Institute of Tech.)
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Date Time 2012-03-07 13:20:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2011-138 
Volume (vol) IEICE-111 
Number (no) no.450 
Page pp.109-114 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2012-02-28 

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