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Paper Abstract and Keywords
Presentation 2012-03-07 10:45
Equivalence Checking Method of Timed Logic Formulae for Design Verification of Single-Flux Quantum Circuits
Takahiro Kawaguchi (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) VLD2011-135
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes an equivalence checking method of timed logic formulae for reducing number of
states in verification of single-flux-quantum circuits. Proposed verification method deal with variables at different
times appeared in timed logic formulae as state variables. The verification of single-flux-quantum circuits can be
achieved with small states.
Keyword (in Japanese) (See Japanese page) 
(in English) single-flux-quantum circuit / equivalence checking / timed logic formulae / / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 450, VLD2011-135, pp. 91-96, March 2012.
Paper # VLD2011-135 
Date of Issue 2012-02-28 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2011-135

Conference Information
Committee VLD  
Conference Date 2012-03-06 - 2012-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) B-con Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Methodologies for System-on-a-chip 
Paper Information
Registration To VLD 
Conference Code 2012-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Equivalence Checking Method of Timed Logic Formulae for Design Verification of Single-Flux Quantum Circuits 
Sub Title (in English)  
Keyword(1) single-flux-quantum circuit  
Keyword(2) equivalence checking  
Keyword(3) timed logic formulae  
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1st Author's Name Takahiro Kawaguchi  
1st Author's Affiliation Nagoya University (Nagoya Univ.)
2nd Author's Name Kazuyoshi Takagi  
2nd Author's Affiliation Kyoto University (Kyoto Univ.)
3rd Author's Name Naofumi Takagi  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
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Speaker Author-1 
Date Time 2012-03-07 10:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2011-135 
Volume (vol) vol.111 
Number (no) no.450 
Page pp.91-96 
#Pages
Date of Issue 2012-02-28 (VLD) 


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