Paper Abstract and Keywords |
Presentation |
2012-01-20 15:10
An Evaluation of An FPGA Based on Synchronous/Asynchronous Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Shota Ishihara, Ryoto Tsuchiya, Michitaka Kameyama (Tohoku Univ.) ICD2011-142 Link to ES Tech. Rep. Archives: ICD2011-142 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents an FPGA architecture that combines synchronous and asynchronous architectures. Datapath components such as logic blocks and switch blocks are designed so as to run in asynchronous and synchronous modes. Moreover, a logic block is presented that implements area-efficient First-in-first-out(FIFO) interfaces, which are usually used for communication between synchronous and asynchronous logic cores. The FPGA based on the hybrid architecture is fabricated in a 65nm process. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / Reconfigurable VLSI / Self-timed architecture / Delay-insensitive architecture / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 388, ICD2011-142, pp. 93-96, Jan. 2012. |
Paper # |
ICD2011-142 |
Date of Issue |
2012-01-12 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2011-142 Link to ES Tech. Rep. Archives: ICD2011-142 |
Conference Information |
Committee |
ICD IPSJ-ARC |
Conference Date |
2012-01-19 - 2012-01-20 |
Place (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2012-01-ICD-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An Evaluation of An FPGA Based on Synchronous/Asynchronous Hybrid Architecture |
Sub Title (in English) |
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Keyword(1) |
FPGA |
Keyword(2) |
Reconfigurable VLSI |
Keyword(3) |
Self-timed architecture |
Keyword(4) |
Delay-insensitive architecture |
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1st Author's Name |
Yoshiya Komatsu |
1st Author's Affiliation |
Tohoku University (Tohoku Univ.) |
2nd Author's Name |
Masanori Hariyama |
2nd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
3rd Author's Name |
Shota Ishihara |
3rd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
4th Author's Name |
Ryoto Tsuchiya |
4th Author's Affiliation |
Tohoku University (Tohoku Univ.) |
5th Author's Name |
Michitaka Kameyama |
5th Author's Affiliation |
Tohoku University (Tohoku Univ.) |
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Speaker |
Author-1 |
Date Time |
2012-01-20 15:10:00 |
Presentation Time |
30 minutes |
Registration for |
ICD |
Paper # |
ICD2011-142 |
Volume (vol) |
vol.111 |
Number (no) |
no.388 |
Page |
pp.93-96 |
#Pages |
4 |
Date of Issue |
2012-01-12 (ICD) |