Paper Abstract and Keywords |
Presentation |
2011-12-16 14:50
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure Yohei Umeki, Shusuke Yoshimoto, Takurou Amashita, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) ICD2011-134 Link to ES Tech. Rep. Archives: ICD2011-134 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5–4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SRAM / soft error / multiple-bit upset / single-event upset / error correction coding / alpha particle / neutron particle / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 352, ICD2011-134, pp. 161-166, Dec. 2011. |
Paper # |
ICD2011-134 |
Date of Issue |
2011-12-08 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2011-134 Link to ES Tech. Rep. Archives: ICD2011-134 |
Conference Information |
Committee |
ICD |
Conference Date |
2011-12-15 - 2011-12-16 |
Place (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2011-12-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure |
Sub Title (in English) |
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Keyword(1) |
SRAM |
Keyword(2) |
soft error |
Keyword(3) |
multiple-bit upset |
Keyword(4) |
single-event upset |
Keyword(5) |
error correction coding |
Keyword(6) |
alpha particle |
Keyword(7) |
neutron particle |
Keyword(8) |
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1st Author's Name |
Yohei Umeki |
1st Author's Affiliation |
Kobe University (Kobe Univ.) |
2nd Author's Name |
Shusuke Yoshimoto |
2nd Author's Affiliation |
Kobe University (Kobe Univ.) |
3rd Author's Name |
Takurou Amashita |
3rd Author's Affiliation |
Kobe University (Kobe Univ.) |
4th Author's Name |
Hiroshi Kawaguchi |
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Kobe University (Kobe Univ.) |
5th Author's Name |
Masahiko Yoshimoto |
5th Author's Affiliation |
Kobe University/JST CREST (Kobe Univ./JST) |
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Speaker |
Author-1 |
Date Time |
2011-12-16 14:50:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
ICD2011-134 |
Volume (vol) |
vol.111 |
Number (no) |
no.352 |
Page |
pp.161-166 |
#Pages |
6 |
Date of Issue |
2011-12-08 (ICD) |
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