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| Presentation | 2011-11-30 09:25 A Priority-Aware On-Chip Network Router for Reducing Priority Inversions Yujiro Sasagawa, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.)  CPSY2011-50 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With advances in fabrication technology, the number of cores on a chip multiprocessor (CMP) increases, and packet-switched Network-on-Chip (NoC) is used for connecting them efficiently. Supporting QoS and real-time system on CMP requires priority-aware NoC that prioritizes high priority packets. Priority inversion occurs at highly-loaded priority-aware NoC, and it reduces system performance. In this paper, we proposed multiple techniques for mitigating priority inversion, and implemented these techniques in on-chip routers. Simulation was performed with three traffic patterns, and we evaluated average latency, jitter and maximum latency of high and low priority packets. Our evaluations show all techniques implemented in this paper mitigated priority inversion. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | On-chip networks / Network-on-Chip (NoC) / priority / priority inversion / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 328, CPSY2011-50, pp. 41-46, Nov. 2011. | |
| Paper # | CPSY2011-50 | |
| Date of Issue | 2011-11-22 (CPSY) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2011-50 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2011-11-28 - 2011-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | NewWelCity Miyazaki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Priority-Aware On-Chip Network Router for Reducing Priority Inversions |
| Sub Title (in English) | |
| Keyword(1) | On-chip networks |
| Keyword(2) | Network-on-Chip (NoC) |
| Keyword(3) | priority |
| Keyword(4) | priority inversion |
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| Keyword(6) | |
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| 1st Author's Name | Yujiro Sasagawa |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Hiroki Matsutani |
| 2nd Author's Affiliation | Keio University (Keio Univ.) |
| 3rd Author's Name | Nobuyuki Yamasaki |
| 3rd Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-11-30 09:25:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | CPSY2011-50 |
| Volume (vol) | vol.111 |
| Number (no) | no.328 |
| Page | pp.41-46 |
| #Pages | 6 |
| Date of Issue | 2011-11-22 (CPSY) |
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