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| Presentation | 2011-11-30 10:30 On the design for testability method using Time to Digital Converter for detecting delay faults Hiroyuki Makimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima)  VLD2011-84 DC2011-60 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We propose the design for testability method for detecting delay fault that can form a TDC(Time-to-Digital Converter) to detect small delay faults. In recent deep sub-micron(DSM) ICs, some faults do not behave like conventional stuck-at fault model and hard to be detected. Since most of open and short defects result in circuit delay, detecting delay faults is important for testing DSM ICs. In this paper, we propose a boundary scan cell that can form a TDC to observe the delay caused by detects. We evaluate the delay detection circuit by simulation. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | design for testability / delay fault / delay detection circuit / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 325, DC2011-60, pp. 185-190, Nov. 2011. | |
| Paper # | DC2011-60 | |
| Date of Issue | 2011-11-21 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2011-84 DC2011-60 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2011-11-28 - 2011-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | NewWelCity Miyazaki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On the design for testability method using Time to Digital Converter for detecting delay faults |
| Sub Title (in English) | |
| Keyword(1) | design for testability |
| Keyword(2) | delay fault |
| Keyword(3) | delay detection circuit |
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| 1st Author's Name | Hiroyuki Makimoto |
| 1st Author's Affiliation | University of Tokushima graduate school (Univ. of Tokushima) |
| 2nd Author's Name | Hiroyuki Yotsuyanagi |
| 2nd Author's Affiliation | University of Tokushima graduate school (Univ. of Tokushima) |
| 3rd Author's Name | Masaki Hashizume |
| 3rd Author's Affiliation | University of Tokushima graduate school (Univ. of Tokushima) |
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| Speaker | Author-1 |
| Date Time | 2011-11-30 10:30:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2011-84, DC2011-60 |
| Volume (vol) | vol.111 |
| Number (no) | no.324(VLD), no.325(DC) |
| Page | pp.185-190 |
| #Pages | 6 |
| Date of Issue | 2011-11-21 (VLD, DC) |
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