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| Presentation | 2011-11-30 11:20 A Method of Thermal Uniformity Control During BIST Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST)  VLD2011-86 DC2011-62 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Along with the improvement in semiconductor technology, it is important to ensure product quality that small delay defects caused by manufacturing variables and in-field degradation are detected. These defects cause delay shift. These defects must be detected by delay test. However, delay shift is caused not only by defects but also by environmental conditions such as temperature. If circuit's temperature is varied temporally and/or spatially, it would be difficult to detect the delay shift caused only by defects. This paper proposes a method of thermal uniformity control during BIST for accurate delay test. The proposed method first adds a mask circuit to the output of each scan FF of a circuit. Then the mask circuits are controlled so that the power consumption of the combinational circuit is adjusted to a uniform temperature without impact on test application time and fault coverage. Experimental results on benchmark circuits show that the proposed method can achieve thermal uniformity during BIST. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | thermal-uniformity / built-in self test (BIST) / delay test / scan cell gateing / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 325, DC2011-62, pp. 197-202, Nov. 2011. | |
| Paper # | DC2011-62 | |
| Date of Issue | 2011-11-21 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2011-86 DC2011-62 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2011-11-28 - 2011-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | NewWelCity Miyazaki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Method of Thermal Uniformity Control During BIST |
| Sub Title (in English) | |
| Keyword(1) | thermal-uniformity |
| Keyword(2) | built-in self test (BIST) |
| Keyword(3) | delay test |
| Keyword(4) | scan cell gateing |
| Keyword(5) | |
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| 1st Author's Name | Eri Murata |
| 1st Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 2nd Author's Name | Satoshi Ohtake |
| 2nd Author's Affiliation | Oita University (Oita Univ.) |
| 3rd Author's Name | Yasuhiko Nakashima |
| 3rd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
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| Speaker | Author-1 |
| Date Time | 2011-11-30 11:20:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2011-86, DC2011-62 |
| Volume (vol) | vol.111 |
| Number (no) | no.324(VLD), no.325(DC) |
| Page | pp.197-202 |
| #Pages | 6 |
| Date of Issue | 2011-11-21 (VLD, DC) |
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