Paper Abstract and Keywords |
Presentation |
2011-11-30 09:25
Measurements and Co-Simulation of On-Chip and On-Boad AC Power Noise in Digital Integrated Circuits Kumpei Yoshikawa, Yuta Sasaki (Kobe Univ.), Kouji Ichikawa (DENSO), Yoshiyuki Saito (Panasonic), Makoto Nagata (Kobe Univ./CREST,JST) CPM2011-163 ICD2011-95 Link to ES Tech. Rep. Archives: CPM2011-163 ICD2011-95 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Power noise of an integrated circuit (IC) chip is dominantly characterized by the frequency-domain impedance of a chip-package-board integrated power delivery network (PDN) and the operating frequency of circuits. A 65 nm CMOS chip embedding a high precision on-chip waveform capturer clearly exhibits the relation of AC power noise components with the parallel resonance seen from on-chip digital circuits. On-chip voltage noise measured by the waveform capturer and on-board current noise by a near-field magnetic field probe are also experimentally related to each other, in the context of the resonance. In addition, fast power current analysis uses a capacitor charging model of digital circuits and embodies accurate co-simulation of AC power noise, along with a chip-package-board integrated PDN impedance model. A predictive measure in the design of IC chips is provided toward on-chip power supply integrity (PSI) as well as off-chip electromagnetic compatibility (EMC). |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
power noise / noise simulation / power integrity / magnetic probe / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 327, ICD2011-95, pp. 73-78, Nov. 2011. |
Paper # |
ICD2011-95 |
Date of Issue |
2011-11-21 (CPM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
CPM2011-163 ICD2011-95 Link to ES Tech. Rep. Archives: CPM2011-163 ICD2011-95 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2011-11-28 - 2011-11-30 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
NewWelCity Miyazaki |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2010 -New Field of VLSI Design- |
Paper Information |
Registration To |
ICD |
Conference Code |
2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Measurements and Co-Simulation of On-Chip and On-Boad AC Power Noise in Digital Integrated Circuits |
Sub Title (in English) |
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Keyword(1) |
power noise |
Keyword(2) |
noise simulation |
Keyword(3) |
power integrity |
Keyword(4) |
magnetic probe |
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1st Author's Name |
Kumpei Yoshikawa |
1st Author's Affiliation |
Kobe University (Kobe Univ.) |
2nd Author's Name |
Yuta Sasaki |
2nd Author's Affiliation |
Kobe University (Kobe Univ.) |
3rd Author's Name |
Kouji Ichikawa |
3rd Author's Affiliation |
DENSO CORPORATION (DENSO) |
4th Author's Name |
Yoshiyuki Saito |
4th Author's Affiliation |
Panasonic Corporation (Panasonic) |
5th Author's Name |
Makoto Nagata |
5th Author's Affiliation |
Kobe University/CREST,JST (Kobe Univ./CREST,JST) |
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Speaker |
Author-1 |
Date Time |
2011-11-30 09:25:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
CPM2011-163, ICD2011-95 |
Volume (vol) |
vol.111 |
Number (no) |
no.326(CPM), no.327(ICD) |
Page |
pp.73-78 |
#Pages |
6 |
Date of Issue |
2011-11-21 (CPM, ICD) |
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