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| Presentation | 2011-11-29 10:15 A BIST-Aided Scan Test using Shifting Inverter Code and a TPG Method for Test Data Reduction Yasuhiko Okada, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima)  VLD2011-74 DC2011-50 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | BIST-aided scan test (BAST) has been proposed as one of the techniques that enhance scan-based BIST.The BAST architecture can achieve high fault coverage by applying ATPG patterns to a circuit through the inverter block that flips some bits in random pattern generated by LFSR. In this paper, we propose a BAST architecture that utilizes compatible flip-flops in configuring scan chains and includes an inverter block that can shift inverter code to reduce test data. We also propose an ATPG method for our BAST that assigns the inconflicting values to the compatible flip-flops to reduce test data by increasing the correlation between ATPG and PRPG patterns. We also show the effectiveness of our method by the experimental results for ISCAS 89 and ITC99 benchmark circuits. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | BAST / test data reduction / test pattern generation / scan chain configuration / compatible flip-flops / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 325, DC2011-50, pp. 133-138, Nov. 2011. | |
| Paper # | DC2011-50 | |
| Date of Issue | 2011-11-21 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2011-74 DC2011-50 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2011-11-28 - 2011-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | NewWelCity Miyazaki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A BIST-Aided Scan Test using Shifting Inverter Code and a TPG Method for Test Data Reduction |
| Sub Title (in English) | |
| Keyword(1) | BAST |
| Keyword(2) | test data reduction |
| Keyword(3) | test pattern generation |
| Keyword(4) | scan chain configuration |
| Keyword(5) | compatible flip-flops |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yasuhiko Okada |
| 1st Author's Affiliation | The University of Tokushima (Univ. of Tokushima) |
| 2nd Author's Name | Hiroyuki Yotsuyanagi |
| 2nd Author's Affiliation | The University of Tokushima (Univ. of Tokushima) |
| 3rd Author's Name | Masaki Hashizume |
| 3rd Author's Affiliation | The University of Tokushima (Univ. of Tokushima) |
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| Speaker | Author-1 |
| Date Time | 2011-11-29 10:15:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2011-74, DC2011-50 |
| Volume (vol) | vol.111 |
| Number (no) | no.324(VLD), no.325(DC) |
| Page | pp.133-138 |
| #Pages | 6 |
| Date of Issue | 2011-11-21 (VLD, DC) |
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