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| Presentation | 2011-11-29 13:50 Power Estimation of Variable Stages Pipeline Processor Using Power Gating Technique Masaki Tanaka, Takahiro Sasaki, Tomoyuki Nakabayashi, Kazuhiko Ohno, Toshio Kondo (Mie Univ)  CPSY2011-45 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Recently, the increase of an energy consumption of mobile computers caused by performance enhancement becomes one serious problem. Therefore, many researches for low energy and high performance computing are carring out. In order to reduce the energy consumption, a variable stages pipeline architecture (VSP), which dynamically varies the pipeline depth according to workload, is proposed. Although the VSP is effective in dynamic power, it is ineffective in leakage power.This paper applies power gating technique to a part of branch predictor in the VSP to reduce leakage power and prevent performance degradation. According to evaluation result,proposal techinique can improves 3.2% energy-delay-products. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Low-power processor / variable stages pipeline / pipeline unification / power gating / branch predictor / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 328, CPSY2011-45, pp. 15-20, Nov. 2011. | |
| Paper # | CPSY2011-45 | |
| Date of Issue | 2011-11-22 (CPSY) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2011-45 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2011-11-28 - 2011-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | NewWelCity Miyazaki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power Estimation of Variable Stages Pipeline Processor Using Power Gating Technique |
| Sub Title (in English) | |
| Keyword(1) | Low-power processor |
| Keyword(2) | variable stages pipeline |
| Keyword(3) | pipeline unification |
| Keyword(4) | power gating |
| Keyword(5) | branch predictor |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Masaki Tanaka |
| 1st Author's Affiliation | Mie University (Mie Univ) |
| 2nd Author's Name | Takahiro Sasaki |
| 2nd Author's Affiliation | Mie University (Mie Univ) |
| 3rd Author's Name | Tomoyuki Nakabayashi |
| 3rd Author's Affiliation | Mie University (Mie Univ) |
| 4th Author's Name | Kazuhiko Ohno |
| 4th Author's Affiliation | Mie University (Mie Univ) |
| 5th Author's Name | Toshio Kondo |
| 5th Author's Affiliation | Mie University (Mie Univ) |
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| Speaker | Author-1 |
| Date Time | 2011-11-29 13:50:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | CPSY2011-45 |
| Volume (vol) | vol.111 |
| Number (no) | no.328 |
| Page | pp.15-20 |
| #Pages | 6 |
| Date of Issue | 2011-11-22 (CPSY) |
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