Paper Abstract and Keywords |
Presentation |
2011-11-29 14:40
Implementation of an FU Array Accelerator and its Analysis Mitsutoshi Saito, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPM2011-159 ICD2011-91 Link to ES Tech. Rep. Archives: CPM2011-159 ICD2011-91 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We have previously proposed Linear Array Pipeline Processor (LAPP), which can map an inner loop of conventional VLIW codes onto Function Unit (FU) array and use minimum required FUs to exploit performance per watt. In the development of LAPP, we have evaluated logic verification by a software simulation first, and the processor realizability on FPGA. Afterwards, we have evaluated the delay time on ASIC. In this paper, we have evaluated the chip area and clock frequency of ASIC(0.18um CMOS process)from viewpoint of the realizability. The result shows that LAPP implemented with slow process (125 ℃, 1.62V) transistor model can operate at 71.4MHz. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FU array / processor development environment / ASIC prototyping / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 327, ICD2011-91, pp. 53-58, Nov. 2011. |
Paper # |
ICD2011-91 |
Date of Issue |
2011-11-21 (CPM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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CPM2011-159 ICD2011-91 Link to ES Tech. Rep. Archives: CPM2011-159 ICD2011-91 |
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