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| Presentation | 2011-11-29 09:50 A Scan Chain Construction Method to Reduce Test Data Volume on BAST Yun Chen, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)  VLD2011-73 DC2011-49 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | BAST is one of techniques which are combined ATPG and BIST to reduce the amount of test data while maintaining the high test quality. On BAST architecture, a bit-flipping technique is used to convert pseudo-random patterns to deterministic patterns. In order to reduce test data volume and test application time, it is necessary to reduce the number of bit-flippings. In this paper, we propose a scan chain construction method which determines connection forms between scan FFs to reduce the number of bit-flippings in pseudo-random patterns. A scan chain construction method is used as the post-processing of a don’t care identification for a random-pattern-resistant fault set and a matching. The reduction ratios of bit-flipping are evaluated for ITC’99 benchmark circuits. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | BAST architecture / don’t care Identification / bit-flipping reduction / scan chain construction / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 325, DC2011-49, pp. 127-132, Nov. 2011. | |
| Paper # | DC2011-49 | |
| Date of Issue | 2011-11-21 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2011-73 DC2011-49 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2011-11-28 - 2011-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | NewWelCity Miyazaki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Scan Chain Construction Method to Reduce Test Data Volume on BAST |
| Sub Title (in English) | |
| Keyword(1) | BAST architecture |
| Keyword(2) | don’t care Identification |
| Keyword(3) | bit-flipping reduction |
| Keyword(4) | scan chain construction |
| Keyword(5) | |
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| 1st Author's Name | Yun Chen |
| 1st Author's Affiliation | Nihon University (Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University (Nihon Univ.) |
| 3rd Author's Name | Masayoshi Yoshimura |
| 3rd Author's Affiliation | Kyushu University (Kyushu Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-11-29 09:50:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2011-73, DC2011-49 |
| Volume (vol) | vol.111 |
| Number (no) | no.324(VLD), no.325(DC) |
| Page | pp.127-132 |
| #Pages | 6 |
| Date of Issue | 2011-11-21 (VLD, DC) |
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