Paper Abstract and Keywords |
Presentation |
2011-11-28 16:05
CMOS Op-amp Offset Calibration Technique Using a Closed Loop Offset Amplifier and Compact Resistor String DAC Hiroyuki Morimoto, Hiroaki Goto (KIT), Hajime Fujiwara (NJR), Kazuyuki Nakamura (KIT) VLD2011-65 DC2011-41 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper describes the development of a circuit system that enables the offset calibration of an op-amp circuit after production. A closed-loop feedback system was developed to realize high-speed and accurate offset calibration action. For the D/A converter which occupies most of the area for the additional calibration circuit, the Folded-Alternated Resistor String DAC was developed. This reduced the area by more than 50% and realized low power consumption while maintaining the same accuracy as a conventional type of DAC. The fabrication with standard 0.35µm CMOS, followed by actual measurement, has confirmed that the offset can be confined to no more than 1.5mV using the new calibration circuit. With this technique, miniaturization of a whole op-amp system can be achieved, because the layout size of each circuit consisting of op-amps can be reduced when using this offset correction circuit. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Op-amp / offset / calibration / D/A converter / resistor string / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 324, VLD2011-65, pp. 79-84, Nov. 2011. |
Paper # |
VLD2011-65 |
Date of Issue |
2011-11-21 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2011-65 DC2011-41 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2011-11-28 - 2011-11-30 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
NewWelCity Miyazaki |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2010 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
CMOS Op-amp Offset Calibration Technique Using a Closed Loop Offset Amplifier and Compact Resistor String DAC |
Sub Title (in English) |
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Keyword(1) |
Op-amp |
Keyword(2) |
offset |
Keyword(3) |
calibration |
Keyword(4) |
D/A converter |
Keyword(5) |
resistor string |
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1st Author's Name |
Hiroyuki Morimoto |
1st Author's Affiliation |
Kyushu Institute of Technology (KIT) |
2nd Author's Name |
Hiroaki Goto |
2nd Author's Affiliation |
Kyushu Institute of Technology (KIT) |
3rd Author's Name |
Hajime Fujiwara |
3rd Author's Affiliation |
New Japan Radio Co., Ltd. (NJR) |
4th Author's Name |
Kazuyuki Nakamura |
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Kyushu Institute of Technology (KIT) |
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Speaker |
Author-1 |
Date Time |
2011-11-28 16:05:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2011-65, DC2011-41 |
Volume (vol) |
vol.111 |
Number (no) |
no.324(VLD), no.325(DC) |
Page |
pp.79-84 |
#Pages |
6 |
Date of Issue |
2011-11-21 (VLD, DC) |
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