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| Presentation | 2011-11-28 15:10 An Acceleration Method for Power Grid Analysis using Block-Iterative Algorithm Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.)  VLD2011-63 DC2011-39 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Because of its extremely large size, power grid analysis has been a computationally challenging problem both in terms of runtime and memory usage. LU factorization has been widely used to analyze voltage drop simulations due to its stability, but contiguous technology scaling demands even more efficient calculation methods. In this paper, application of block-iterative method, which combines LU factorization and iterative method, is proposed for efficient analysis of power grid analysis. Automatic adjustment of relaxation factor in successive over-relaxation method and block decomposition algorithm are proposed. Evaluation results are also presented. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Power grid analysis / Block-iterative method / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 324, VLD2011-63, pp. 67-71, Nov. 2011. | |
| Paper # | VLD2011-63 | |
| Date of Issue | 2011-11-21 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2011-63 DC2011-39 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2011-11-28 - 2011-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | NewWelCity Miyazaki |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2010 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2011-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Acceleration Method for Power Grid Analysis using Block-Iterative Algorithm |
| Sub Title (in English) | |
| Keyword(1) | Power grid analysis |
| Keyword(2) | Block-iterative method |
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| 1st Author's Name | Takumi Morishita |
| 1st Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 2nd Author's Name | Hiroshi Tsutsui |
| 2nd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 3rd Author's Name | Hiroyuki Ochi |
| 3rd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 4th Author's Name | Takashi Sato |
| 4th Author's Affiliation | Kyoto University (Kyoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-11-28 15:10:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2011-63, DC2011-39 |
| Volume (vol) | vol.111 |
| Number (no) | no.324(VLD), no.325(DC) |
| Page | pp.67-71 |
| #Pages | 5 |
| Date of Issue | 2011-11-21 (VLD, DC) |
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