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| Presentation | 2011-10-25 15:05 Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption Junshi Takata (Kyushu Univ.), Tohru Ishihara (Kyoto Univ.), Koji Inoue (Kyushu Univ.)  SIP2011-76 ICD2011-79 IE2011-75 Link to ES Tech. Rep. Archives: ICD2011-79 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The paper proposes a technique which simultaneously finds the optimal cache way allocation and code placement for given multiple tasks running on a single core processor. It reduces the energy consumption in a set-associative cache by activating only a single cache way at a time and deactivating the remaining cache ways. The technique also reduces the number of cache misses by changing the code placement in a main memory, which results in a reduction of the energy consumption in the main memory as well as the reduction of total execution time. Experiments using a commercial embedded processor demonstrate that the technique reduces the total energy consumption in the target processor system by 17\% at the best case compared to the energy of the system which does not apply our technique. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | embedded system / multi task / cache memory / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 111, no. 258, ICD2011-79, pp. 89-94, Oct. 2011. | |
| Paper # | ICD2011-79 | |
| Date of Issue | 2011-10-17 (SIP, ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SIP2011-76 ICD2011-79 IE2011-75 Link to ES Tech. Rep. Archives: ICD2011-79 |
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| Conference Information | |
| Committee | ICD IE SIP IPSJ-SLDM |
| Conference Date | 2011-10-24 - 2011-10-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ｉｃｈｉｎｏｂｏ(Sendai) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2011-10-ICD-IE-SIP-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption |
| Sub Title (in English) | |
| Keyword(1) | embedded system |
| Keyword(2) | multi task |
| Keyword(3) | cache memory |
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| 1st Author's Name | Junshi Takata |
| 1st Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 2nd Author's Name | Tohru Ishihara |
| 2nd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 3rd Author's Name | Koji Inoue |
| 3rd Author's Affiliation | Kyushu University (Kyushu Univ.) |
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| Speaker | Author-1 |
| Date Time | 2011-10-25 15:05:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | SIP2011-76, ICD2011-79, IE2011-75 |
| Volume (vol) | vol.111 |
| Number (no) | no.257(SIP), no.258(ICD), no.259(IE) |
| Page | pp.89-94 |
| #Pages | 6 |
| Date of Issue | 2011-10-17 (SIP, ICD, IE) |
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