Paper Abstract and Keywords |
Presentation |
2011-10-24 14:20
Three-Dimensional Accelerator Architecture for Image Recognition Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) SIP2011-63 ICD2011-66 IE2011-62 Link to ES Tech. Rep. Archives: ICD2011-66 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Image recognition used widely in several areas needs high-performance and low power processor. Accelerator is an effective method of high-performance and low-energy. Because conventional accelerator architecture is fixed while features of image recognition is wide variety, it is difficult for conventional accelerator that high-performance and low-energy execution. This paper describes adaptive accelerator architecture that we call NIMD/MIMD accelerator. NIMD/MIMD accelerator is able to select NIMD (No Instruction streams, Multiple Data streams) execution or MIMD (Multiple Instruction streams, Multiple Data streams) execution. In evaluation used model, we find that NIMD/MIMD accelerator is 7% faster and 40% lower energy than MIMD accelerator. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Accelerator / 3D-IC / Reconfigurable-Processor / Image Recognition / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 258, ICD2011-66, pp. 7-12, Oct. 2011. |
Paper # |
ICD2011-66 |
Date of Issue |
2011-10-17 (SIP, ICD, IE) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SIP2011-63 ICD2011-66 IE2011-62 Link to ES Tech. Rep. Archives: ICD2011-66 |
Conference Information |
Committee |
ICD IE SIP IPSJ-SLDM |
Conference Date |
2011-10-24 - 2011-10-25 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Ichinobo(Sendai) |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2011-10-ICD-IE-SIP-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Three-Dimensional Accelerator Architecture for Image Recognition |
Sub Title (in English) |
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Keyword(1) |
Accelerator |
Keyword(2) |
3D-IC |
Keyword(3) |
Reconfigurable-Processor |
Keyword(4) |
Image Recognition |
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1st Author's Name |
Shinya Ueno |
1st Author's Affiliation |
Kyushu University (Kyushu Univ.) |
2nd Author's Name |
Gauthier Lovic Eric |
2nd Author's Affiliation |
Kyushu University (Kyushu Univ.) |
3rd Author's Name |
Koji Inoue |
3rd Author's Affiliation |
Kyushu University (Kyushu Univ.) |
4th Author's Name |
Kazuaki Murakami |
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Kyushu University (Kyushu Univ.) |
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Speaker |
Author-1 |
Date Time |
2011-10-24 14:20:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
SIP2011-63, ICD2011-66, IE2011-62 |
Volume (vol) |
vol.111 |
Number (no) |
no.257(SIP), no.258(ICD), no.259(IE) |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2011-10-17 (SIP, ICD, IE) |
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