IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2011-09-30 11:10
Efficient Encoding for Quasi-Cyclic LDPC Codes with Rank Deficient Parity Check Matrices
Haruka Obata, Hironori Uchikawa (Toshiba) IT2011-29
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents an efficient encoding method for quasi-cyclic low-density parity-check (QC-LDPC) codes with rank deficient parity check matrices. In general, QC-LDPC codes can be encoded with simple shift registers. However, when QC-LDPC codes with rank deficient parity check matrices are encoded based on Richardson and Urbanke (R&U) method which is one of the most efficient encoding methods, the encoder cannot be implemented with shift registers because these generator matrices are not in circulant forms. By allowing generator matrices in semi-systematic forms, the proposed method provides about 30 percent reduction of the encoding complexity by using R&U method so that the generator matrices remain in circulant forms.
Keyword (in Japanese) (See Japanese page) 
(in English) Quasi-cyclic low-densiy parity-check code / encoder / rank deficient parity check matrix / Richardson and Urbanke method / / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 220, IT2011-29, pp. 35-40, Sept. 2011.
Paper # IT2011-29 
Date of Issue 2011-09-22 (IT) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF IT2011-29

Conference Information
Committee IT  
Conference Date 2011-09-29 - 2011-09-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Tokyo Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To IT 
Conference Code 2011-09-IT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Efficient Encoding for Quasi-Cyclic LDPC Codes with Rank Deficient Parity Check Matrices 
Sub Title (in English)  
Keyword(1) Quasi-cyclic low-densiy parity-check code  
Keyword(2) encoder  
Keyword(3) rank deficient parity check matrix  
Keyword(4) Richardson and Urbanke method  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Haruka Obata  
1st Author's Affiliation Toshiba Corporation (Toshiba)
2nd Author's Name Hironori Uchikawa  
2nd Author's Affiliation Toshiba Corporation (Toshiba)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2011-09-30 11:10:00 
Presentation Time 25 minutes 
Registration for IT 
Paper # IT2011-29 
Volume (vol) vol.111 
Number (no) no.220 
Page pp.35-40 
#Pages
Date of Issue 2011-09-22 (IT) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan