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Paper Abstract and Keywords
Presentation 2011-09-27 09:45
Evaluation of Net-based Move in Placement for a Memory-based Reconfigurable Device MPLD
Masato Inagi, Masatoshi Nakamura, Tetsuo Hironaka (Hiroshima City Univ.), Takashi Ishiguro (Taiyo Yuden) VLD2011-47
Abstract (in Japanese) (See Japanese page) 
(in English) FPGAs realize a target circuit by realizing logic cells by LUTs and connecting wires among the logic cells by switch blocks. However, a switch block requires a large area and many routing layers, and it was reported that the area ratio of switch blocks in a recent FPGA exceeds 90%. Thus, we have proposed an area-efficient reconfigurable device, MPLD,
which has no switch blocks. An MPLD consists of an array of multiple-output LUTs (MLUTs), which realize both logic cells and wire connections. When placing a circuit on an MPLD using a standard method based on simulated annealing, a logic cell is randomly selected and replaced, and then the placement is evaluated to decide if the placement is accepted or not. This method, however, rarely translates regionally optimized sub-circuits to adjust their positions. In this study, to shorten the
distance between good placement solutions, we propose a net-based move in neighbor solution generation which translates the logic cells connected by a target net, and evaluate its effectiveness by experiments.
Keyword (in Japanese) (See Japanese page) 
(in English) MPLD / FPGA / Placement / Simulated annealing / Move / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 216, VLD2011-47, pp. 37-42, Sept. 2011.
Paper # VLD2011-47 
Date of Issue 2011-09-19 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2011-47

Conference Information
Committee VLD  
Conference Date 2011-09-26 - 2011-09-27 
Place (in Japanese) (See Japanese page) 
Place (in English) University of Aizu 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Physical-level Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2011-09-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of Net-based Move in Placement for a Memory-based Reconfigurable Device MPLD 
Sub Title (in English)  
Keyword(1) MPLD  
Keyword(2) FPGA  
Keyword(3) Placement  
Keyword(4) Simulated annealing  
Keyword(5) Move  
1st Author's Name Masato Inagi  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Masatoshi Nakamura  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Tetsuo Hironaka  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Takashi Ishiguro  
4th Author's Affiliation Taiyo Yuden Co., Ltd (Taiyo Yuden)
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Date Time 2011-09-27 09:45:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2011-47 
Volume (vol) IEICE-111 
Number (no) no.216 
Page pp.37-42 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2011-09-19 

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