Paper Abstract and Keywords |
Presentation |
2011-09-26 14:20
Development Modeling Compiler and Operation Test for the Hardware Design Generate HDL from UML State Machine Diagram Daiki Kano, Ryota Yamazaki (Tokai Univ.), Naohiko Shimizu (Tokai Univ./IP ARCH, Inc.) RECONF2011-27 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper describes the UML modeling compiler and operation test using that.The UML modeling compiler performs automatic creation of the hardware description language which can be logic synthesis using the UML class diagrams and the UML activity diagrams and the UML state machine diagrams,and it performs hardware design all with the system level.We show the rule to make the UML state machine diagram correspond to the NSL language. In this rule, we developed UML modeling compiler STA2NSL which generates NSL detail from state machine diagram.We detail operation state of hardware to UML state machine diagram.We designed hardware which needs state transition using this way, and we verify to operate hardware on the FPGA. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
UML / Class Diagram / Activity Diagram / State Machine Diagram / Hardware Design / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 218, RECONF2011-27, pp. 31-36, Sept. 2011. |
Paper # |
RECONF2011-27 |
Date of Issue |
2011-09-19 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2011-27 |
Conference Information |
Committee |
RECONF |
Conference Date |
2011-09-26 - 2011-09-27 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Nagoya Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2011-09-RECONF |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Development Modeling Compiler and Operation Test for the Hardware Design Generate HDL from UML State Machine Diagram |
Sub Title (in English) |
* |
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UML |
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Class Diagram |
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Activity Diagram |
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State Machine Diagram |
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Hardware Design |
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1st Author's Name |
Daiki Kano |
1st Author's Affiliation |
Tokai University (Tokai Univ.) |
2nd Author's Name |
Ryota Yamazaki |
2nd Author's Affiliation |
Tokai University (Tokai Univ.) |
3rd Author's Name |
Naohiko Shimizu |
3rd Author's Affiliation |
Tokai University/IP ARCH, Inc. (Tokai Univ./IP ARCH, Inc.) |
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Speaker |
Author-1 |
Date Time |
2011-09-26 14:20:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2011-27 |
Volume (vol) |
vol.111 |
Number (no) |
no.218 |
Page |
pp.31-36 |
#Pages |
6 |
Date of Issue |
2011-09-19 (RECONF) |
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