Paper Abstract and Keywords |
Presentation |
2011-09-26 11:10
Feasibility study of nonvolatile reconfiguralbe device by using a standard CMOS logic process Shuji Kunimitsu, Mamoru Terauchi, Kazuya Tanigawa, Tetsuo Hironaka (HCU), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN) RECONF2011-23 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we consider the realization of nonvolatile PLD, based on the new recongurable device
architecture MPLD. MPLD (Memory based PLD) realize LUT and switch function equivalent in FPGA by using
MLUT ( Multi-directional Look Up Tables) as its fundamental element. In the conventional implementation SRAM
cell arrays are used in implementing MLUTs. In this paper, we replace the SRAM cell with nonvolatile memory
cells to implement the nonvolatile MPLD. In that case, simply replacing the memory cell arrays are not enough
to implement non-volatile MPLD. This is because MPLD requires asynchronous memory read operations on logic
mode, and high voltages on writing the non-volatile memory cell arrays. Moreover, there is a problem that the cost
goes up by using a
ash memory process. So we considered designing the MLUT by using a nonvolatile memory
that is possible to manufacture in the standard CMOS logic process, and designed the control circuits for it. From
the simulation result, we conrmed MPLD with a nonvolatile characteristic can function as a normal MPLD.
Key words MPLD, memory, nonvolatile,standard logic process,simulation |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
MPLD / memory / nonvolatile / standard logic process / simulation / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 218, RECONF2011-23, pp. 7-12, Sept. 2011. |
Paper # |
RECONF2011-23 |
Date of Issue |
2011-09-19 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2011-23 |
Conference Information |
Committee |
RECONF |
Conference Date |
2011-09-26 - 2011-09-27 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Nagoya Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2011-09-RECONF |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Feasibility study of nonvolatile reconfiguralbe device by using a standard CMOS logic process |
Sub Title (in English) |
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Keyword(1) |
MPLD |
Keyword(2) |
memory |
Keyword(3) |
nonvolatile |
Keyword(4) |
standard logic process |
Keyword(5) |
simulation |
Keyword(6) |
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Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Shuji Kunimitsu |
1st Author's Affiliation |
Hiroshima City Univercity (HCU) |
2nd Author's Name |
Mamoru Terauchi |
2nd Author's Affiliation |
Hiroshima City Univercity (HCU) |
3rd Author's Name |
Kazuya Tanigawa |
3rd Author's Affiliation |
Hiroshima City Univercity (HCU) |
4th Author's Name |
Tetsuo Hironaka |
4th Author's Affiliation |
Hiroshima City Univercity (HCU) |
5th Author's Name |
Masayuki Sato |
5th Author's Affiliation |
TAIYO YUDEN CO., LTD. (TAIYO YUDEN) |
6th Author's Name |
Takashi Ishiguro |
6th Author's Affiliation |
TAIYO YUDEN CO., LTD. (TAIYO YUDEN) |
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Speaker |
Author-1 |
Date Time |
2011-09-26 11:10:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2011-23 |
Volume (vol) |
vol.111 |
Number (no) |
no.218 |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2011-09-19 (RECONF) |
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