Paper Abstract and Keywords |
Presentation |
2011-07-04 17:20
Design method of system LSI with low power device Ryosuke Suzuki, Shigeyoshi Watanabe (Shonan Inst. Tech.) SDM2011-70 Link to ES Tech. Rep. Archives: SDM2011-70 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Design method of system LSI such as inverter, NAND, and full adder with low power tunnel transistor has been described. Pattern area of system LSI with plane tunnel transistor is larger than that with conventional planar CMOS transistor. By introducing FinFET type tunnel transistor pattern area of system LSI can be reduced to smaller value compared with that using conventional planar CMOS transistor. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Low power / tunnel type transistor / pattern layout / system LSI / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 114, SDM2011-70, pp. 115-119, July 2011. |
Paper # |
SDM2011-70 |
Date of Issue |
2011-06-27 (SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2011-70 Link to ES Tech. Rep. Archives: SDM2011-70 |
Conference Information |
Committee |
SDM |
Conference Date |
2011-07-04 - 2011-07-04 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
VBL, Nagoya Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Science and Technology for Dielectric Thin Films for Electron Devices |
Paper Information |
Registration To |
SDM |
Conference Code |
2011-07-SDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design method of system LSI with low power device |
Sub Title (in English) |
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Low power |
Keyword(2) |
tunnel type transistor |
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pattern layout |
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system LSI |
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1st Author's Name |
Ryosuke Suzuki |
1st Author's Affiliation |
Shonan Institute of Technology (Shonan Inst. Tech.) |
2nd Author's Name |
Shigeyoshi Watanabe |
2nd Author's Affiliation |
Shonan Institute of Technology (Shonan Inst. Tech.) |
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Speaker |
Author-1 |
Date Time |
2011-07-04 17:20:00 |
Presentation Time |
20 minutes |
Registration for |
SDM |
Paper # |
SDM2011-70 |
Volume (vol) |
vol.111 |
Number (no) |
no.114 |
Page |
pp.115-119 |
#Pages |
5 |
Date of Issue |
2011-06-27 (SDM) |