Paper Abstract and Keywords |
Presentation |
2011-07-01 14:10
Accelerating and Memory Reduction of 2D Continuous Dynamic Programming Processing Using Dedicated Hardware Junko Tazawa, Yuichi Yaguchi, Toshiaki Miyazaki, Ryuichi Oka (Univ. of Aizu) CAS2011-25 VLD2011-32 SIP2011-54 MSS2011-25 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We are designing a hardware accelerator for 2DCDP (2-dimensional continuous dynamic programming) that is an optimal pixel matching algorithm between an input image and a reference one to realize a spotting recognition. The spotting recognition can perform image recognition and segmentation simultaneously. To realize the optimal pixel matching, the whole pixels in the reference image must be matched to the part of the input image nonlinearly, and the matching process requires huge computation power and memory. In this paper, we overview the hardware accelerator to perform 2DCDP effectively. In the proposed architecture, parallelized accumulated local minimum calculators and toggle memory structure are newly introduced to reduce computation cost and memory. In addition, we show some preliminary estimated results for its performance and size of the required memory. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Continuous DP / Full Pixel Matching / Image Recognition / Spotting Recognition / Toggle Memory Structure / FPGA / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 103, VLD2011-32, pp. 141-146, June 2011. |
Paper # |
VLD2011-32 |
Date of Issue |
2011-06-23 (CAS, VLD, SIP, MSS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2011-25 VLD2011-32 SIP2011-54 MSS2011-25 |
Conference Information |
Committee |
MSS CAS VLD SIP |
Conference Date |
2011-06-30 - 2011-07-01 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa-Ken-Seinen-Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2011-06-MSS-CAS-VLD-SIP |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Accelerating and Memory Reduction of 2D Continuous Dynamic Programming Processing Using Dedicated Hardware |
Sub Title (in English) |
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Keyword(1) |
Continuous DP |
Keyword(2) |
Full Pixel Matching |
Keyword(3) |
Image Recognition |
Keyword(4) |
Spotting Recognition |
Keyword(5) |
Toggle Memory Structure |
Keyword(6) |
FPGA |
Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Junko Tazawa |
1st Author's Affiliation |
The University of Aizu (Univ. of Aizu) |
2nd Author's Name |
Yuichi Yaguchi |
2nd Author's Affiliation |
The University of Aizu (Univ. of Aizu) |
3rd Author's Name |
Toshiaki Miyazaki |
3rd Author's Affiliation |
The University of Aizu (Univ. of Aizu) |
4th Author's Name |
Ryuichi Oka |
4th Author's Affiliation |
The University of Aizu (Univ. of Aizu) |
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Speaker |
Author-1 |
Date Time |
2011-07-01 14:10:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
CAS2011-25, VLD2011-32, SIP2011-54, MSS2011-25 |
Volume (vol) |
vol.111 |
Number (no) |
no.102(CAS), no.103(VLD), no.104(SIP), no.105(MSS) |
Page |
pp.141-146 |
#Pages |
6 |
Date of Issue |
2011-06-23 (CAS, VLD, SIP, MSS) |
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