Paper Abstract and Keywords |
Presentation |
2011-04-19 10:55
0.5-V FinFET SRAM Using Dynamic-Threshold-Voltage Pass Gates Shin-ichi O'uchi, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara (AIST) ICD2011-11 Link to ES Tech. Rep. Archives: ICD2011-11 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This article presents a FinFET SRAM which salvages malfunctioned bits caused by random variation. In the presenting SRAM array, pass gates (PGs) of a 6-transistor SRAM cell consist of tunable-threshold-voltage (Vt) FinFETs. The Vt of those PGs is gradually lowered from a initial value during the read process. Once a datum is detected from a sense amplifier, the Vt is restored to the initial value. By this dynamic threshold-voltage control of PGs, the best Vt for each cell is automatically chosen, and the trade-off relationship between read speed and read margin is optimized in each cell. This technique is effective to reduce supply voltage in a scaled process. The experimental and simulation results suggest that this technique will enable 0.5V operation at read delay within 2ns in an Lg-20nm low-standby-power (LSTP) technology |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
variable-tthreshold-voltage FinFET / 6T-SRAM / random variation / SNM / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 6, ICD2011-11, pp. 59-63, April 2011. |
Paper # |
ICD2011-11 |
Date of Issue |
2011-04-11 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2011-11 Link to ES Tech. Rep. Archives: ICD2011-11 |
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