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Presentation 2011-04-19 09:55
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers
Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe (Toshiba) ICD2011-9 Link to ES Tech. Rep. Archives: ICD2011-9
Abstract (in Japanese) (See Japanese page) 
(in English) A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static random access memory (SRAM) sense amplifiers (SA). The SA timing variation attributable to the random variation of transistor threshold voltage (VTH) is reduced by a sufficient count of replica cells, and replica bitline delay is digitized and multiplied to adjust it to the target SA timing. The variation of the generated SA timing was 41% smaller than that with a conventional technique and cycle time was reduced 20% at the supply voltage (VDD) of 0.6V in 40nm CMOS technology with this scheme.
Keyword (in Japanese) (See Japanese page) 
(in English) SRAM / Sense Amplifier (SA) / Timing Generation / Random Variation / Replica Bitline Delay / / /  
Reference Info. IEICE Tech. Rep., vol. 111, no. 6, ICD2011-9, pp. 49-54, April 2011.
Paper # ICD2011-9 
Date of Issue 2011-04-11 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2011-9 Link to ES Tech. Rep. Archives: ICD2011-9

Conference Information
Committee ICD  
Conference Date 2011-04-18 - 2011-04-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kobe University Takigawa Memorial Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Memory Device Technologies 
Paper Information
Registration To ICD 
Conference Code 2011-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers 
Sub Title (in English)  
Keyword(1) SRAM  
Keyword(2) Sense Amplifier (SA)  
Keyword(3) Timing Generation  
Keyword(4) Random Variation  
Keyword(5) Replica Bitline Delay  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yusuke Niki  
1st Author's Affiliation Toshiba Corporation (Toshiba)
2nd Author's Name Atsushi Kawasumi  
2nd Author's Affiliation Toshiba Corporation (Toshiba)
3rd Author's Name Azuma Suzuki  
3rd Author's Affiliation Toshiba Corporation (Toshiba)
4th Author's Name Yasuhisa Takeyama  
4th Author's Affiliation Toshiba Corporation (Toshiba)
5th Author's Name Osamu Hirabayashi  
5th Author's Affiliation Toshiba Corporation (Toshiba)
6th Author's Name Keiichi Kushida  
6th Author's Affiliation Toshiba Corporation (Toshiba)
7th Author's Name Fumihiko Tachibana  
7th Author's Affiliation Toshiba Corporation (Toshiba)
8th Author's Name Yuki Fujimura  
8th Author's Affiliation Toshiba Corporation (Toshiba)
9th Author's Name Tomoaki Yabe  
9th Author's Affiliation Toshiba Corporation (Toshiba)
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Speaker Author-1 
Date Time 2011-04-19 09:55:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2011-9 
Volume (vol) vol.111 
Number (no) no.6 
Page pp.49-54 
#Pages
Date of Issue 2011-04-11 (ICD) 


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