Paper Abstract and Keywords |
Presentation |
2011-04-19 09:55
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe (Toshiba) ICD2011-9 Link to ES Tech. Rep. Archives: ICD2011-9 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static random access memory (SRAM) sense amplifiers (SA). The SA timing variation attributable to the random variation of transistor threshold voltage (VTH) is reduced by a sufficient count of replica cells, and replica bitline delay is digitized and multiplied to adjust it to the target SA timing. The variation of the generated SA timing was 41% smaller than that with a conventional technique and cycle time was reduced 20% at the supply voltage (VDD) of 0.6V in 40nm CMOS technology with this scheme. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SRAM / Sense Amplifier (SA) / Timing Generation / Random Variation / Replica Bitline Delay / / / |
Reference Info. |
IEICE Tech. Rep., vol. 111, no. 6, ICD2011-9, pp. 49-54, April 2011. |
Paper # |
ICD2011-9 |
Date of Issue |
2011-04-11 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2011-9 Link to ES Tech. Rep. Archives: ICD2011-9 |